公开(公告)号：US20190042979A1

公开(公告)日：2019-02-07

申请号：US16021704

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Raghuveer Devulapalli ,  Kelly Hammond ,  Yonghong Huang ,  Srinivas Pandruvada ,  Rahul Unnikrishnan Nair ,  Arjan Van De Ven ,  Denis Vladimirov ,  Qin Wang

IPC: G06N99/00 ,  G05B19/406

Abstract: An embodiment of a semiconductor package apparatus may include technology to learn thermal behavior information of a system based on input information including one or more of processor information, thermal information, and cooling information, and provide information to adjust one or more of a parameter of a processor and a parameter of a cooling subsystem based on the learned thermal behavior information and the input information. Other embodiments are disclosed and claimed.

公开(公告)号：US11520498B2

公开(公告)日：2022-12-06

申请号：US17116991

申请日：2020-12-09

Applicant: Intel Corporation

Inventor： Nadav Bonen ,  Sridhar Muthrasanallur ,  Srinivas Pandruvada ,  Vishwanath Somayaji ,  Prashant Kodali

IPC: G06F3/06

Abstract: Logical memory is divided into two regions. Data in the first region is always retained. The first region of memory is designated online (or powered on) and is not offlined during standby or low power mode. The second region is the rest of the memory which can be potentially placed in non-self-refresh mode during standby by offlining the memory region. Content in the second region can be moved to the first region or can be flushed to another memory managed by the operating system. When the first region does not have enough space to accommodate data from the second region, the operating system can increase the logical size of the first region. Retaining the content of the first region by putting that region in self-refresh and saving power in the second region by not putting it in self-refresh is performed by an improved Partial Array Self Refresh scheme.

公开(公告)号：US20210191753A1

公开(公告)日：2021-06-24

申请号：US16723691

申请日：2019-12-20

Applicant: Intel Corporation

Inventor： Jacob Pan ,  Ashok Raj ,  Srinivas Pandruvada

IPC: G06F9/48 ,  G06F9/54

Abstract: Apparatus, method, and machine-readable medium to provide performance state matching between source and target processors based on inter-processor interrupts. An exemplary apparatus includes a target processor to execute a receiving task at a first performance level and a source processor to execute a sending task at a second performance level higher than the first performance level. The sending task is to store interrupt routing data indicating a pairing between the sending task and the receiving task into a memory location and that the sending task is to dispatch work to be processed by the receiving task. The apparatus further includes a performance management unit to detect the pairing between the sending task and the receiving task based on the interrupt routing data and responsively adjust the performance level of the target processor from the first performance level to the second performance level based, at least in part, on the pairing.

公开(公告)号：US20200278914A1

公开(公告)日：2020-09-03

申请号：US16647563

申请日：2018-08-27

Applicant: Intel Corporation

Inventor： HISHAM ABU SALAH ,  Arthur Leonard Brown ,  Russell J. Fenger ,  Deepak Samuel Kirubakaran ,  Asit K. Mallick ,  Jacob Jun Pan ,  Srinivas Pandruvada ,  Efraim Rotem ,  Arjan Van De Ven ,  Eliezer Weissmann ,  Rafal J. Wysocki

IPC: G06F11/34 ,  G06F11/30 ,  G06F9/48 ,  G06F9/50

Abstract: In an embodiment, a processor includes multiple processing engines and a power control unit. The power control unit is to: maintain a first utilization metric for a first processing engine; detect a thread transfer from a first processing engine to a second processing engine; and generate, using the first utilization metric for the first processing engine, a second utilization metric for a second processing engine. Other embodiments are described and claimed.

公开(公告)号：US20190213153A1

公开(公告)日：2019-07-11

申请号：US15864290

申请日：2018-01-08

Applicant: Intel Corporation

Inventor： Jacob Jun Pan ,  Ashok Raj ,  Srinivas Pandruvada

IPC: G06F13/24

Abstract: In an embodiment, a processor for performance state adjustment includes a plurality of processing engines (PEs), a power control unit, and an input/output memory management unit (IOMMU). The IOMMU is to determine a destination PE for a user interrupt based on mapping data of the IOMMU, and to send a notification of the user interrupt to the power control unit. The notification indicates the destination PE for the user interrupt. The power control unit is to adjust a performance state of the destination PE in response to the notification of the user interrupt. Other embodiments are described and claimed.

公开(公告)号：US20210405892A1

公开(公告)日：2021-12-30

申请号：US17116991

申请日：2020-12-09

Applicant: Intel Corporation

Inventor： Nadav Bonen ,  Sridhar Muthrasanallur ,  Srinivas Pandruvada ,  Vishwanath Somayaji ,  Prashant Kodali

IPC: G06F3/06

Abstract: Logical memory is divided into two regions. Data in the first region is always retained. The first region of memory is designated online (or powered on) and is not offlined during standby or low power mode. The second region is the rest of the memory which can be potentially placed in non-self-refresh mode during standby by offlining the memory region. Content in the second region can be moved to the first region or can be flushed to another memory managed by the operating system. When the first region does not have enough space to accommodate data from the second region, the operating system can increase the logical size of the first region. Retaining the content of the first region by putting that region in self-refresh and saving power in the second region by not putting it in self-refresh is performed by an improved Partial Array Self Refresh scheme.

公开(公告)号：US20200218677A1

公开(公告)日：2020-07-09

申请号：US16819283

申请日：2020-03-16

Applicant: Intel Corporation

Inventor： Jacob Jun Pan ,  Ashok Raj ,  Srinivas Pandruvada

IPC: G06F13/24

Abstract: In an embodiment, a processor for performance state adjustment includes a plurality of processing engines (PEs), a power control unit, and an input/output memory management unit (IOMMU). The IOMMU is to determine a destination PE for a user interrupt based on mapping data of the IOMMU, and to send a notification of the user interrupt to the power control unit. The notification indicates the destination PE for the user interrupt. The power control unit is to adjust a performance state of the destination PE in response to the notification of the user interrupt. Other embodiments are described and claimed.

公开(公告)号：US10599596B2

公开(公告)日：2020-03-24

申请号：US15864290

申请日：2018-01-08

Applicant: Intel Corporation

Inventor： Jacob Jun Pan ,  Ashok Raj ,  Srinivas Pandruvada

IPC: G06F13/10 ,  G06F13/24 ,  G06F15/80 ,  G06F9/30

Abstract: In an embodiment, a processor for performance state adjustment includes a plurality of processing engines (PEs), a power control unit, and an input/output memory management unit (IOMMU). The IOMMU is to determine a destination PE for a user interrupt based on mapping data of the IOMMU, and to send a notification of the user interrupt to the power control unit. The notification indicates the destination PE for the user interrupt. The power control unit is to adjust a performance state of the destination PE in response to the notification of the user interrupt. Other embodiments are described and claimed.

公开(公告)号：US11775336B2

公开(公告)日：2023-10-03

申请号：US16723691

申请日：2019-12-20

Applicant: Intel Corporation

Inventor： Jacob Pan ,  Ashok Raj ,  Srinivas Pandruvada

IPC: G06F9/48 ,  G06F9/54 ,  G06F15/163 ,  G06F15/173

CPC classification number: G06F9/4812 ,  G06F9/544 ,  G06F15/163 ,  G06F15/17325 ,  G06F2209/486

Abstract: Apparatus, method, and machine-readable medium to provide performance state matching between source and target processors based on inter-processor interrupts. An exemplary apparatus includes a target processor to execute a receiving task at a first performance level and a source processor to execute a sending task at a second performance level higher than the first performance level. The sending task is to store interrupt routing data indicating a pairing between the sending task and the receiving task into a memory location and that the sending task is to dispatch work to be processed by the receiving task. The apparatus further includes a performance management unit to detect the pairing between the sending task and the receiving task based on the interrupt routing data and responsively adjust the performance level of the target processor from the first performance level to the second performance level based, at least in part, on the pairing.

公开(公告)号：US11354213B2

公开(公告)日：2022-06-07

申请号：US16647563

申请日：2018-08-27

Applicant: Intel Corporation

Inventor： Hisham Abu Salah ,  Arthur Leonard Brown ,  Russell J. Fenger ,  Deepak Samuel Kirubakaran ,  Asit K. Mallick ,  Jun Pan ,  Srinivas Pandruvada ,  Efraim Rotem ,  Arjan Van De Ven ,  Eliezer Weissmann ,  Rafal J. Wysocki

IPC: G06F9/46 ,  G06F11/34 ,  G06F11/30 ,  G06F9/48 ,  G06F9/50

Abstract: In an embodiment, a processor includes multiple processing engines and a power control unit. The power control unit is to: maintain a first utilization metric for a first processing engine; detect a thread transfer from a first processing engine to a second processing engine; and generate, using the first utilization metric for the first processing engine, a second utilization metric for a second processing engine. Other embodiments are described and claimed.