公开(公告)号：US10049971B2

公开(公告)日：2018-08-14

申请号：US15478064

申请日：2017-04-03

Applicant: Intel Corporation

Inventor： Thomas J. De Bonis ,  Lilia May ,  Rajen S. Sidhu ,  Mukul P. Renavikar ,  Ashay A. Dani ,  Edward R. Prack ,  Carl L. Deppisch ,  Anna M. Prakash ,  James C. Matayabas ,  Jason Jieping Zhang ,  Srinivasa R. Aravamudhan ,  Chang Lin

IPC: H01L21/00 ,  H01L23/498 ,  H01L25/065 ,  H01L23/31 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L25/00 ,  H01L23/00

Abstract: An apparatus is described that includes a substrate and a mold compound disposed on the substrate. The semiconductor die is embedded within the mold compound and is electrically coupled to lands on the substrate. Solder balls are disposed around the semiconductor die on the substrate. Each of the solder balls have a solid coating thereon. The solid coating contains a cleaning agent to promote its solder ball's coalescence with another solder ball. Respective vias are formed in the mold compound that expose the solder balls and their respective solid coatings. In combined or alternate embodiments outer edges of the mold compound have smaller thickness than regions of the mold compound between the vias and the semiconductor die. In combined or alternate embodiments micro-channels exist between the solder balls and the mold compound.

公开(公告)号：US20240063134A1

公开(公告)日：2024-02-22

申请号：US18260805

申请日：2021-02-26

Applicant: Intel Corporation

Inventor： Xiaoning Ye ,  Pooya Tadayon ,  Wenzhi Wang ,  Srinivasa R. Aravamudhan ,  Nathan Somnang Tan ,  Brett Daniel Grossman

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L23/5386 ,  H01L25/0655 ,  H01L23/5383 ,  H01L23/49894 ,  H01L23/49877 ,  H01L2224/16225 ,  H01L24/16

Abstract: Disclosed herein are integrated circuit (IC) supports with microstrips, and related embodiments. For example, an IC support may include a plurality of microstrips and a plurality of conductive segments. Individual ones of the conductive segments may be at least partially over at least two microstrips, a dielectric material may be between the plurality of microstrips and the plurality of conductive segments, and an individual conductive segment may have a conductivity that is close to or less than a conductivity of a conductive line of an individual microstrip.

公开(公告)号：US20180288877A1

公开(公告)日：2018-10-04

申请号：US15476130

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Srinivasa R. Aravamudhan ,  Christopher D. Combs

IPC: H05K1/18 ,  H05K1/11 ,  H05K3/34

Abstract: Apparatus and method associated with surface structures of compute component packages are disclosed herein. In embodiments, an apparatus may include a plurality of structures provided on a surface of a compute component package, wherein the plurality of structures are to be used to attach and electrically couple the compute component package to another device, and wherein a structure of the plurality of structures includes first and second portions, the second portion disposed further from the surface than the first portion, and the first portion to comprise a material different from the second portion.

公开(公告)号：US11830846B2

公开(公告)日：2023-11-28

申请号：US16424227

申请日：2019-05-28

Applicant: Intel Corporation

Inventor： Feroz Mohammad ,  Srinivasa R. Aravamudhan

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/34

CPC classification number: H01L24/81 ,  H01L23/345 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/98 ,  H01L2224/16238 ,  H01L2224/81234 ,  H01L2224/81815

Abstract: Embodiments herein relate to systems, apparatuses, or processes for coupling or decoupling two substrates by heating pins on one of the substrates and either inserting or withdrawing the heated pins from solder elements on a BGA. In particular, by heating a plurality of pins on a first side of a first substrate, where the plurality of pins are substantially perpendicular to a plane of the substrate, inserting the heated plurality of pins into BGA attached to a second substrate where the BGA includes a plurality of solder elements aligned with the plurality of pins and where the heated plurality of pins melt the plurality of solder elements upon insertion. The inserted plurality of pins physically and/or electrically couple the first substrate and the second substrate.

公开(公告)号：US10573580B2

公开(公告)日：2020-02-25

申请号：US15476130

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Srinivasa R. Aravamudhan ,  Christopher D. Combs

IPC: H01L23/52 ,  H01L23/488 ,  H05K3/34

Abstract: Apparatus and method associated with surface structures of compute component packages are disclosed herein. In embodiments, an apparatus may include a plurality of structures provided on a surface of a compute component package, wherein the plurality of structures are to be used to attach and electrically couple the compute component package to another device, and wherein a structure of the plurality of structures includes first and second portions, the second portion disposed further from the surface than the first portion, and the first portion to comprise a material different from the second portion.

公开(公告)号：US20170207152A1

公开(公告)日：2017-07-20

申请号：US15478064

申请日：2017-04-03

Applicant: Intel Corporation

Inventor： Thomas J. De Bonis ,  Lilia May ,  Rajen S. Sidhu ,  Mukul P. Renavikar ,  Ashay A. Dani ,  Edward R. Prack ,  Carl L. Deppisch ,  Anna M. Prakash ,  James C. Matayabas ,  Jason Jieping Zhang ,  Srinivasa R. Aravamudhan ,  Chang Lin

IPC: H01L23/498 ,  H01L23/31 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L21/565 ,  H01L21/76802 ,  H01L23/3128 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/13023 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/37001 ,  H01L2924/00

Abstract: An apparatus is described that includes a substrate and a mold compound disposed on the substrate. The semiconductor die is embedded within the mold compound and is electrically coupled to lands on the substrate. Solder balls are disposed around the semiconductor die on the substrate. Each of the solder balls have a solid coating thereon. The solid coating contains a cleaning agent to promote its solder ball's coalescence with another solder ball. Respective vias are formed in the mold compound that expose the solder balls and their respective solid coatings. In combined or alternate embodiments outer edges of the mold compound have smaller thickness than regions of the mold compound between the vias and the semiconductor die. In combined or alternate embodiments micro-channels exist between the solder balls and the mold compound.