公开(公告)号：US10980129B2

公开(公告)日：2021-04-13

申请号：US16819899

申请日：2020-03-16

Applicant: Intel Corporation

Inventor： Sri Chaitra Jyotsna Chavali ,  Amruthavalli Pallavi Alur ,  Wei-Lun Kane Jen ,  Sriram Srinivasan

IPC: H05K1/02 ,  H05K1/09 ,  H05K1/11 ,  H05K1/16 ,  H05K1/18 ,  H05K3/00 ,  H05K3/02 ,  H05K3/04 ,  H05K3/10 ,  H05K3/20 ,  H05K3/30 ,  H05K3/36 ,  H05K3/40 ,  H05K3/42 ,  H05K3/44 ,  H05K3/46

Abstract: An asymmetric electronic substrate and method of making the substrate includes forming a first layer on each opposing major surface of a removable carrier layer, the first layer being a routing layer, simultaneously laminating the first layers, and building up subsequent layers on layers previously formed and laminated on the removable carrier layer iteratively. The subsequent layers including routing layers and a core layer formed on each side of the removable carrier layer, the core layer including through holes having a larger gauge than through holes included in the routing layers. A number of layers on a first side of the core layer, between the core layer and the carrier layer, is different than a number of layers on a second side of the core layer. The carrier layer is removed to produce two asymmetric substrates, each asymmetric substrate including one of the at least one core layers.

公开(公告)号：US10455685B1

公开(公告)日：2019-10-22

申请号：US16159840

申请日：2018-10-15

Applicant: Intel Corporation

Inventor： Steven A. Klein ,  Kuang Liu ,  Thomas A. Boyd ,  Luis Gil Rangel ,  Muffadal Mukadem ,  Shelby A. Ferguson ,  Francis Toth, Jr. ,  Eric Buddrius ,  Ralph V. Miele ,  Sriram Srinivasan ,  Jeffory L. Smalley

IPC: H01L23/522 ,  H01L23/485 ,  H01L23/32 ,  H05K1/02 ,  H05K3/30 ,  H01R12/70 ,  H05K7/10 ,  H01L23/367 ,  H05K3/36

Abstract: An electronic device may include a circuit board, and the circuit board may include a dielectric material. A socket may be coupled to a first side of the circuit board, and the socket may be configured to receive a semiconductor package. A backing plate may be positioned on a second side of the circuit board. A spacer may be positioned between the backing plate and the circuit board. The spacer may alter the profile of the socket to provide a curved profile to the socket. The spacer may displace a portion of the socket in a first direction, for instance when the spacer is coupled between the backing plate and the circuit board.

公开(公告)号：US20190182955A1

公开(公告)日：2019-06-13

申请号：US15841246

申请日：2017-12-13

Applicant: Intel Corporation

Inventor： Gregorio R. Murtagian ,  Kuang C. Liu ,  Sriram Srinivasan ,  Jeffory L. Smalley ,  Zhichao Zhang

IPC: H05K1/14 ,  H01R12/73 ,  H05K1/11 ,  H05K1/18 ,  H05K1/02 ,  H05K3/36 ,  H05K3/34

Abstract: Electronic device package technology is disclosed. An electronic device package in accordance with the present disclosure can include a package substrate. The electronic device package can also include a processor mounted on the package substrate. Additionally, the electronic device package can include a memory socket mounted on the package substrate and operably coupled to the processor. The memory socket can be operable to removably couple with a memory module and facilitate electrical communication between the processor and the memory module. A memory module can include a plurality of printed circuit boards (PCBs). Each PCB can have a bottom edge and a plurality of contact pads located about the bottom edge. Additionally, the memory module can include a memory device mounted on at least one of the plurality of PCBs and electrically connected to at least one of the pluralities of contact pads to facilitate electrically coupling the memory module with an external electronic component, such as a processor. Associated systems and methods are also disclosed.

公开(公告)号：US20160151850A1

公开(公告)日：2016-06-02

申请号：US15017398

申请日：2016-02-05

Applicant: Intel Corporation

Inventor： Deepak V. Kulkarni ,  Carl L. Deppisch ,  Leonel R. Arana ,  Gregory S. Constable ,  Sriram Srinivasan

IPC: B23K1/00 ,  B23K1/20 ,  H01L23/367

CPC classification number: B23K1/0016 ,  B23K1/20 ,  B23K1/203 ,  B23K3/085 ,  H01L23/3675 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/16251 ,  Y10T428/12222

Abstract: Methods and associated structures of forming a package structure including forming a low melting point solder material on a solder resist opening location of an IHS keep out zone, forming a sealant in a non SRO keep out zone region; attaching the IHS to the sealant, and curing the sealant, wherein a solder joint is formed between the IHS and the low melting point solder material.

Abstract translation: 形成封装结构的方法和相关结构包括在IHS的阻焊剂开口位置上形成低熔点焊料材料，从而在非SRO保护区域内形成密封剂; 将IHS连接到密封剂上，并固化密封剂，其中在IHS和低熔点焊料材料之间形成焊接接头。

公开(公告)号：US20160043488A1

公开(公告)日：2016-02-11

申请号：US14922791

申请日：2015-10-26

Applicant: Intel Corporation

Inventor： Joshua D Heppner ,  Sriram Srinivasan

IPC: H01R12/70 ,  G01R1/04 ,  H01R43/20 ,  H05K1/18 ,  G06F1/16

CPC classification number: H01R12/7076 ,  G01R1/0433 ,  G01R1/0466 ,  G01R1/06727 ,  G01R1/06733 ,  G06F1/1613 ,  H01R12/714 ,  H01R12/716 ,  H01R13/2471 ,  H01R43/205 ,  H05K1/181 ,  Y10T29/49204

Abstract: An apparatus includes a plurality of contact elements to provide electrical continuity between an integrated circuit and an electronic subassembly, wherein a contact element includes a spring element and a separate lead element, wherein the spring element is arranged to be substantially vertically slidable over at least a portion of the lead element in response to a force applied to the contact element.

Abstract translation: 一种装置包括多个接触元件，以在集成电路和电子子组件之间提供电连续性，其中接触元件包括弹簧元件和单独的引线元件，其中弹簧元件布置成基本上可垂直滑动至少一个 引导元件的一部分响应于施加到接触元件的力。

公开(公告)号：US20230207525A1

公开(公告)日：2023-06-29

申请号：US17561845

申请日：2021-12-24

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Sriram Srinivasan ,  Christopher Pelto ,  Gwang-Soo Kim ,  Nitin Deshpande ,  Omkar Karhade

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/3185 ,  H01L24/08 ,  H01L24/16 ,  H01L24/73 ,  H01L2224/08145 ,  H01L2224/16145 ,  H01L2224/73253 ,  H01L2225/06568

Abstract: A packaged device comprises first die stack and a third die. The first die stack includes a first die comprising first conductive contacts each at a first side of the first die, and a second die comprising second conductive contacts each at a second side of the second die. First solder bonds which each extend to a respective one of the first conductive contacts. The third die comprises third conductive contacts each at a third side of the third die. The third die is coupled to the first die stack via second solder bonds which each extend to a respective one of the second conductive contacts, and to a respective one of the third conductive contacts. Each die of the first die stack is coupled to each of a respective one or more other dies of the first die stack via respective hybrid bonds.

公开(公告)号：US10784204B2

公开(公告)日：2020-09-22

申请号：US16305012

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： Kemal Aygun ,  Richard J. Dischler ,  Jeff C. Morriss ,  Zhiguo Qian ,  Wilfred Gomes ,  Yu Amos Zhang ,  Ram S. Viswanath ,  Rajasekaran Swaminathan ,  Sriram Srinivasan ,  Yidnekachew S. Mekonnen ,  Sanka Ganesan ,  Eduard Roytman ,  Mathew J. Manusharow

IPC: H01L23/538 ,  H01L23/522 ,  H01L23/528 ,  H01L23/60 ,  H01L23/00 ,  H01L25/065

Abstract: Integrated circuit (IC) chip die to die channel interconnect configurations (systems and methods for their manufacture) may improve signaling to and through a single ended bus data signal communication channel by including on-die induction structures; on-die interconnect features; on-package first level die bump designs and ground webbing structures; on-package high speed horizontal data signal transmission lines; on-package vertical data signal transmission interconnects; and/or on-package electro-optical (EO) connectors in various die to die interconnect configurations for improved signal connections and transmission through a data signal channel extending through one or more semiconductor device package devices, that may include an electro-optical (EO) connector upon which at least one package device may be mounted, and/or be semiconductor device packages in a package-on-package configuration.

公开(公告)号：US09601848B2

公开(公告)日：2017-03-21

申请号：US14922791

申请日：2015-10-26

Applicant: Intel Corporation

Inventor： Joshua D Heppner ,  Sriram Srinivasan

IPC: H01R12/00 ,  H01R12/70 ,  H01R12/71 ,  H01R13/24 ,  G01R1/04 ,  G06F1/16 ,  H01R43/20 ,  H05K1/18 ,  G01R1/067

CPC classification number: H01R12/7076 ,  G01R1/0433 ,  G01R1/0466 ,  G01R1/06727 ,  G01R1/06733 ,  G06F1/1613 ,  H01R12/714 ,  H01R12/716 ,  H01R13/2471 ,  H01R43/205 ,  H05K1/181 ,  Y10T29/49204

Abstract: An apparatus includes a plurality of contact elements to provide electrical continuity between an integrated circuit and an electronic subassembly, wherein a contact element includes a spring element and a separate lead element, wherein the spring element is arranged to be substantially vertically slidable over at least a portion of the lead element in response to a force applied to the contact element.

公开(公告)号：US09461431B2

公开(公告)日：2016-10-04

申请号：US14751871

申请日：2015-06-26

Applicant: INTEL CORPORATION

Inventor： Gregorio R. Murtagian ,  Bhanu Jaiswal ,  Sriram Srinivasan ,  Michael J. Hill

IPC: H01R11/30 ,  H01R43/20 ,  H01R13/62 ,  H01R43/26 ,  H01R12/73

CPC classification number: H01R43/205 ,  H01R12/73 ,  H01R13/6205 ,  H01R43/26 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49149

Abstract: A mechanism is described for facilitating and employing a magnetic grid array according to one embodiment. A method of embodiments may include engaging, via magnetic force of a magnet, magnetic contacts of a magnetic grid array to substrate lands of a package substrate of an integrated circuit package of a computing system, and disengaging, via a removal lever, the magnetic contacts from the substrate lands.

公开(公告)号：US11901299B2

公开(公告)日：2024-02-13

申请号：US18079753

申请日：2022-12-12

Applicant: Intel Corporation

Inventor： Md Altaf Hossain ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy ,  Robert Sankman ,  Ravindranath V. Mahajan ,  Debendra Mallik ,  Ram S. Viswanath ,  Sandeep B. Sane ,  Sriram Srinivasan ,  Rajat Agarwal ,  Aravind Dasu ,  Scott Weber ,  Ravi Gutala

IPC: H01L23/538 ,  H01L25/18 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/17 ,  H01L25/18 ,  H01L23/481 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2924/381

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.