公开(公告)号：US11494968B2

公开(公告)日：2022-11-08

申请号：US17322677

申请日：2021-05-17

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Prasoonkumar Surti ,  Srivallaba Mysore ,  Subhajit Dasgupta ,  Hiroshi Akiba ,  Eric J. Hoekstra ,  Linda L. Hurd ,  Travis T. Schluessler ,  Daren J. Schmidt

IPC: G06T15/00 ,  G06T15/50 ,  G06T1/20 ,  G06F1/3287 ,  G06F9/54

Abstract: Briefly, in accordance with one or more embodiments, a processor receives an incoming data stream that includes alpha channel data, and a memory stores an application programming interface (API). The API is to route the alpha channel data to a fixed point blending unit to perform one or more blending operations using fixed point representation of the alpha channel data. The API is further to route the incoming data stream to a floating point blending unit to perform operations involving floating point representation of the incoming data.

公开(公告)号：US12190441B2

公开(公告)日：2025-01-07

申请号：US18436522

申请日：2024-02-08

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Abhishek R. Appu ,  Subhajit Dasgupta ,  Srivallaba Mysore ,  Michael J. Norris ,  Vasanth Ranganathan ,  Joydeep Ray

IPC: G06T15/80 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00

Abstract: One embodiment provides for a graphics processing unit comprising a processing cluster to perform multi-rate shading via coarse pixel shading and output shaded coarse pixels for processing by a post-shader pixel processing pipeline.

公开(公告)号：US11670044B2

公开(公告)日：2023-06-06

申请号：US17723328

申请日：2022-04-18

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Abhishek R. Appu ,  Subhajit Dasgupta ,  Srivallaba Mysore ,  Michael J. Norris ,  Vasanth Ranganathan ,  Joydeep Ray

IPC: G06T15/80 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00

CPC classification number: G06T15/80 ,  G06T1/20 ,  G06T1/60 ,  G06T15/005 ,  G06T2210/52

Abstract: One embodiment provides for a graphics processing unit comprising a processing cluster to perform coarse pixel shading and output shaded coarse pixels for processing by a pixel processing pipeline and a render cache to store coarse pixel data for input to or output from a pixel processing pipeline.

公开(公告)号：US20220329835A1

公开(公告)日：2022-10-13

申请号：US17853719

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Satya Yedidi ,  Srivallaba Mysore ,  Shriram Deshpande

IPC: H04N19/423 ,  H04N19/105 ,  H04N19/88 ,  H04N19/176

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to implement predictor prefetching in video encoding. The example apparatus includes processor circuitry to perform operations to instantiate a predictor list generator circuitry and a predictor prefetch circuitry. The example predictor list generator circuitry to obtain predictor candidates indicating memory locations storing reference blocks from a previous block and sort the predictor candidates in a priority order. The example predictor prefetch circuitry to send cache line requests to the memory corresponding to at least some the predictor candidates that satisfy a threshold priority value. The example predictor prefetch circuitry to send the cache line requests to the memory before a reference block winner of the previous block is determined.

公开(公告)号：US11315311B2

公开(公告)日：2022-04-26

申请号：US16922094

申请日：2020-07-07

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Abhishek R. Appu ,  Subhajit Dasgupta ,  Srivallaba Mysore ,  Michael J. Norris ,  Vasanth Ranganathan ,  Joydeep Ray

IPC: G06T15/80 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00

Abstract: One embodiment provides for a graphics processing unit comprising a processing cluster to perform coarse pixel shading and output shaded coarse pixels for processing by a pixel processing pipeline and a render cache to store coarse pixel data for input to or output from pixel processing pipeline.

公开(公告)号：US20220327772A1

公开(公告)日：2022-10-13

申请号：US17723328

申请日：2022-04-18

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Abhishek R. Appu ,  Subhajit Dasgupta ,  Srivallaba Mysore ,  Michael J. Norris ,  Vasanth Ranganathan ,  Joydeep Ray

IPC: G06T15/80 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00

Abstract: One embodiment provides for a graphics processing unit comprising a processing cluster to perform coarse pixel shading and output shaded coarse pixels for processing by a pixel processing pipeline and a render cache to store coarse pixel data for input to or output from a pixel processing pipeline.

公开(公告)号：US20210343064A1

公开(公告)日：2021-11-04

申请号：US17322677

申请日：2021-05-17

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Prasoonkumar Surti ,  Srivallaba Mysore ,  Subhajit Dasgupta ,  Hiroshi Akiba ,  Eric J. Hoekstra ,  Linda L. Hurd ,  Travis T. Schluessler ,  Daren J. Schmidt

IPC: G06T15/00 ,  G06T15/50 ,  G06T1/20 ,  G06F1/3287 ,  G06F9/54

Abstract: Briefly, in accordance with one or more embodiments, a processor receives an incoming data stream that includes alpha channel data, and a memory stores an application programming interface (API). The API is to route the alpha channel data to a fixed point blending unit to perform one or more blending operations using fixed point representation of the alpha channel data. The API is further to route the incoming data stream to a floating point blending unit to perform operations involving floating point representation of the incoming data.

公开(公告)号：US20180308280A1

公开(公告)日：2018-10-25

申请号：US15493214

申请日：2017-04-21

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Abhishek R. Appu ,  Subhajit Dasgupta ,  Srivallaba Mysore ,  Michael J. Norris ,  Vasanth Ranganathan ,  Joydeep Ray

IPC: G06T15/80 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00

Abstract: One embodiment provides for a graphics processing unit comprising a processing cluster to perform coarse pixel shading and output shaded coarse pixels for processing by a pixel processing pipeline and a render cache to store coarse pixel data for input to or output from pixel processing pipeline.

公开(公告)号：US20240221295A1

公开(公告)日：2024-07-04

申请号：US18436522

申请日：2024-02-08

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Abhishek R. Appu ,  Subhajit Dasgupta ,  Srivallaba Mysore ,  Michael J. Norris ,  Vasanth Ranganathan ,  Joydeep Ray

IPC: G06T15/80 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00

CPC classification number: G06T15/80 ,  G06T1/20 ,  G06T1/60 ,  G06T15/005 ,  G06T2210/52

Abstract: One embodiment provides for a graphics processing unit comprising a processing cluster to perform multi-rate shading via coarse pixel shading and output shaded coarse pixels for processing by a post-shader pixel processing pipeline.

公开(公告)号：US11961179B2

公开(公告)日：2024-04-16

申请号：US18305511

申请日：2023-04-24

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Abhishek R. Appu ,  Subhajit Dasgupta ,  Srivallaba Mysore ,  Michael J. Norris ,  Vasanth Ranganathan ,  Joydeep Ray

IPC: G06T15/80 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00

CPC classification number: G06T15/80 ,  G06T1/20 ,  G06T1/60 ,  G06T15/005 ,  G06T2210/52

Abstract: One embodiment provides for a graphics processing unit comprising a processing cluster to perform multi-rate shading via coarse pixel shading and output shaded coarse pixels for processing by a post-shader pixel processing pipeline.