公开(公告)号：US12199142B2

公开(公告)日：2025-01-14

申请号：US17133092

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Siddharth Chouksey ,  Jack T. Kavalieros ,  Stephen M. Cea ,  Ashish Agrawal ,  Willy Rachmady

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

Abstract: Neighboring gate-all-around integrated circuit structures having a conductive contact stressor between epitaxial source or drain regions are described. In an example, a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate. A first gate stack is over the first vertical arrangement of nanowires. A second gate stack is over the second vertical arrangement of nanowires. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. An intervening conductive contact structure is between neighboring ones of the first epitaxial source or drain structures and of the second epitaxial source or drain structures. The intervening conductive contact structure imparts a stress to the neighboring ones of the first epitaxial source or drain structures and of the second epitaxial source or drain structures.

公开(公告)号：US11676965B2

公开(公告)日：2023-06-13

申请号：US16146219

申请日：2018-09-28

Applicant: INTEL CORPORATION

Inventor： Stephen M. Cea ,  Tahir Ghani ,  Anand S. Murthy ,  Biswajeet Guha

IPC: H01L27/092 ,  H01L29/51 ,  H01L29/165 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06 ,  H01L21/308 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H03K19/20

CPC classification number: H01L27/0924 ,  H01L21/3086 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/4232 ,  H01L29/517 ,  H01L29/6681 ,  H01L29/66545 ,  H01L29/785 ,  H03K19/20

Abstract: Fabrication techniques for NMOS and PMOS nanowires leveraging an isolated process flow for NMOS and PMOS nanowires facilitates independent (decoupled) tuning/variation of the respective geometries (i.e., sizing) and chemical composition of NMOS and PMOS nanowires existing in the same process. These independently tunable degrees of freedom are achieved due to fabrication techniques disclosed herein, which enable the ability to individually adjust the width of NMOS and PMOS nanowires as well as the general composition of the material forming these nanowires independently of one another. In the context of nanowire based semiconductors, in which NMOS and PMOS nanowires are incorporated as channel, drain and source regions respectively for NMOS and PMOS nanowire transistors, independent tuning of the NMOS and PMOS nanowires facilitates independent tuning of short-channel effects, gate drive, the width of the transistor dead space capacitance, strain and other performance related characteristics of associated NMOS and PMOS nanowire transistors.

公开(公告)号：US11522072B2

公开(公告)日：2022-12-06

申请号：US17080458

申请日：2020-10-26

Applicant: Intel Corporation

Inventor： Rishabh Mehandru ,  Patrick Morrow ,  Ranjith Kumar ,  Cory E. Weber ,  Seiyon Kim ,  Stephen M. Cea ,  Tahir Ghani

IPC: H01L29/45 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/11 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/108 ,  H01L27/12 ,  H01L29/778

Abstract: Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.

公开(公告)号：US11430868B2

公开(公告)日：2022-08-30

申请号：US16020361

申请日：2018-06-27

Applicant: INTEL CORPORATION

Inventor： Rishabh Mehandru ,  Biswajeet Guha ,  Anupama Bowonder ,  Anand S. Murthy ,  Tahir Ghani ,  Stephen M. Cea

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78 ,  H01L21/74 ,  H01L29/66 ,  H01L29/20 ,  H01L29/161 ,  H01L29/16

Abstract: Integrated circuit structures including a buried etch-stop layer to help control transistor source/drain depth are provided herein. The buried etch-stop layer addresses the issue of the source/drain etch (or epi-undercut (EUC) etch) going below the bottom of the active height of the channel region, as such an issue can result in un-controlled sub-fin leakage that causes power consumption degradation and other undesired performance issues. The buried etch-stop layer is formed below the channel material, such as in the epitaxial stack that includes the channel material, and acts to slow the removal of material after the channel material has been removed when etching to form the source/drain trenches. In other words, the buried etch-stop layer includes different material from the channel material that can be etched, for at least one given etchant, at a relatively slower rate than the channel material to help control the source/drain trench depth.

公开(公告)号：US11049861B2

公开(公告)日：2021-06-29

申请号：US15747692

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Aaron Lilak ,  Patrick Morrow ,  Rishabh Mehandru ,  Donald W. Nelson ,  Stephen M. Cea

IPC: H01L27/108

Abstract: Techniques and mechanisms to provide capacitance with a memory cell of an integrated circuit. In an embodiment, a transistor of the memory cell includes structures variously formed in or on a first side of a semiconductor substrate. After processing to form the transistor structures, thinning is performed to expose a second side of the semiconductor substrate, the second side opposite the first side. Processing in or on the exposed second side of the semiconductor substrate is subsequently performed to form in the semiconductor substrate a capacitor that extends to couple to one of the transistor structures. In another embodiment, the capacitor is coupled to accumulate charge based on activation of a channel of the transistor. The capacitor is further coupled to send charge from the memory cell via the second side.

公开(公告)号：US20210083117A1

公开(公告)日：2021-03-18

申请号：US16642335

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Rishabh Mehandru ,  Stephen M. Cea ,  Tahir Ghani ,  Anand S. Murthy

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/66

Abstract: Techniques and mechanisms to impose stress on a transistor which includes a channel region and a source or drain region each in a fin structure. In an embodiment, a gate structure of the transistor extends over the fin structure, wherein a first spacer portion is at a sidewall of the gate structure and a second spacer portion adjoins the first spacer portion. Either or both of two features are present at or under respective bottom edges of the spacer portions. One of the features includes a line of discontinuity on the fin structure. The other feature includes a concentration of a dopant in the second spacer portion being greater than a concentration of the dopant in the source or drain region. In another embodiment, the fin structure is disposed on a buffer layer, wherein stress on the channel region is imposed at least in part with the buffer layer.

公开(公告)号：US10937665B2

公开(公告)日：2021-03-02

申请号：US16327713

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Harold W. Kennel ,  Patrick Morrow ,  Rishabh Mehandru ,  Stephen M. Cea

IPC: H01L21/322 ,  H01L21/265 ,  H01L21/768 ,  H01L21/38 ,  H01L21/70 ,  H01L23/26

Abstract: Methods and apparatus for gettering impurities in semiconductors are disclosed. A disclosed example multilayered die includes a substrate material, a component layer below the substrate material, and an impurity attractant region disposed in the substrate material.

公开(公告)号：US10529827B2

公开(公告)日：2020-01-07

申请号：US15748842

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Rishabh Mehandru ,  Patrick Morrow ,  Paul B. Fischer ,  Aaron D. Lilak ,  Stephen M. Cea

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L21/8238

Abstract: Embodiments of the invention include vertically oriented long channel transistors and methods of forming such transistors. In one embodiment, a method of forming such a transistor may include forming a fin on a semiconductor substrate. Embodiments may also include forming a spacer over an upper portion of the fin and a lower portion of the fin not covered by the spacer may be exposed. Embodiments may also include forming a gate dielectric layer over the exposed portion of the fin. A gate electrode may then be deposited, according to an embodiment. Embodiments may include exposing a top portion of the fin and forming a first source/drain (S/D) region in the top portion of the fin. The second S/D region may be formed by removing the semiconductor substrate to expose a bottom portion of the fin and forming the second S/D region in the bottom portion of the fin.

公开(公告)号：US20180323195A1

公开(公告)日：2018-11-08

申请号：US15773325

申请日：2015-12-03

Applicant: Intel Corporation

Inventor： Rishabh Mehandru ,  Roza Kotlyar ,  Stephen M. Cea ,  Patrick H. Keys

IPC: H01L27/092 ,  H01L29/10 ,  H01L21/8238

Abstract: Disclosed herein are stacked channel structures for metal oxide semiconductor field effect transistors (MOSFETs) and related circuit elements, computing devices, and methods. For example, a stacked channel structure may include: a semiconductor substrate having a substrate lattice constant; a fin extending away from the semiconductor substrate, the fin having an upper region and a lower region; a first transistor in the lower region, wherein the first transistor has a first channel, the first channel has a first lattice constant, and the first lattice constant is different from the substrate lattice constant; and a second transistor in the upper region, wherein the second transistor has a second channel, the second channel has a second lattice constant, and the second lattice constant is different from the substrate lattice constant.

公开(公告)号：US10026829B2

公开(公告)日：2018-07-17

申请号：US15434981

申请日：2017-02-16

Applicant: Intel Corporation

Inventor： Annalisa Cappellani ,  Stephen M. Cea ,  Tahir Ghani ,  Harry Gomez ,  Jack T. Kavalieros ,  Patrick H. Keys ,  Seiyon Kim ,  Kelin J. Kuhn ,  Aaron D. Lilak ,  Rafael Rios ,  Mayank Sahni

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L29/06 ,  H01L29/775 ,  H01L27/12 ,  B82Y10/00 ,  H01L29/423

Abstract: Semiconductor devices with isolated body portions are described. For example, a semiconductor structure includes a semiconductor body disposed above a semiconductor substrate. The semiconductor body includes a channel region and a pair of source and drain regions on either side of the channel region. An isolation pedestal is disposed between the semiconductor body and the semiconductor substrate. A gate electrode stack at least partially surrounds a portion of the channel region of the semiconductor body.