公开(公告)号：US12108595B2

公开(公告)日：2024-10-01

申请号：US17001525

申请日：2020-08-24

Applicant: Intel Corporation

Inventor： Sumit Ashtekar ,  Rahul Ramaswamy ,  Walid Hafez ,  Hector M. Saavedra Garcia

IPC: H01L21/8238 ,  H01H85/02 ,  H01L29/66 ,  H01L29/78 ,  H10B20/20

CPC classification number: H10B20/20 ,  H01H85/0241 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01H2085/0283

Abstract: A device structure includes a first gate on a first fin, a second gate on a second fin, where the second gate is spaced apart from the first gate by a distance. A fuse spans the distance and is in contact with the first gate and the second gate. A first dielectric is between the first fin and the second fin, where the first dielectric is in contact with, and below, the fuse and a second dielectric is between the first gate and the second gate, where the second dielectric is on the fuse.

公开(公告)号：US20220059552A1

公开(公告)日：2022-02-24

申请号：US17001525

申请日：2020-08-24

Applicant: Intel Corporation

Inventor： Sumit Ashtekar ,  Rahul Ramaswamy ,  Walid Hafez ,  Hector M. Saavedra Garcia

IPC: H01L27/112 ,  H01H85/02 ,  H01L29/78 ,  H01L29/66

Abstract: A device structure includes a first gate on a first fin, a second gate on a second fin, where the second gate is spaced apart from the first gate by a distance. A fuse spans the distance and is in contact with the first gate and the second gate. A first dielectric is between the first fin and the second fin, where the first dielectric is in contact with, and below, the fuse and a second dielectric is between the first gate and the second gate, where the second dielectric is on the fuse.