公开(公告)号：US12081323B2

公开(公告)日：2024-09-03

申请号：US18116957

申请日：2023-03-03

Applicant: Intel Corporation

Inventor： Murugasamy K. Nachimuthu ,  Mohan J. Kumar ,  Vasudevan Srinivasan

IPC: G06F8/65 ,  G02B6/38 ,  G02B6/42 ,  G02B6/44 ,  G06F1/18 ,  G06F1/20 ,  G06F3/06 ,  G06F9/30 ,  G06F9/4401 ,  G06F9/54 ,  G06F12/109 ,  G06F12/14 ,  G06F13/16 ,  G06F13/40 ,  G06F15/16 ,  G06F16/901 ,  G08C17/02 ,  G11C5/02 ,  G11C7/10 ,  G11C11/56 ,  G11C14/00 ,  H03M7/30 ,  H03M7/40 ,  H04B10/25 ,  H04L41/14 ,  H04L43/08 ,  H04L43/0817 ,  H04L43/0876 ,  H04L43/0894 ,  H04L49/00 ,  H04L49/25 ,  H04L49/356 ,  H04L49/45 ,  H04L67/02 ,  H04L67/12 ,  H04L67/306 ,  H04L69/04 ,  H04L69/329 ,  H04Q11/00 ,  H05K7/14 ,  B25J15/00 ,  B65G1/04 ,  G05D23/19 ,  G05D23/20 ,  G06F9/38 ,  G06F9/50 ,  G06F11/14 ,  G06F11/34 ,  G06F12/0862 ,  G06F12/0893 ,  G06F12/10 ,  G06F13/42 ,  G06F15/80 ,  G06Q10/06 ,  G06Q10/0631 ,  G06Q10/087 ,  G06Q10/20 ,  G06Q50/04 ,  G07C5/00 ,  G11C5/06 ,  H04J14/00 ,  H04L9/06 ,  H04L9/14 ,  H04L9/32 ,  H04L12/28 ,  H04L41/02 ,  H04L41/046 ,  H04L41/0813 ,  H04L41/082 ,  H04L41/0896 ,  H04L41/12 ,  H04L41/147 ,  H04L41/5019 ,  H04L43/065 ,  H04L43/16 ,  H04L45/02 ,  H04L45/52 ,  H04L47/24 ,  H04L47/38 ,  H04L47/70 ,  H04L47/765 ,  H04L47/78 ,  H04L47/80 ,  H04L49/15 ,  H04L49/55 ,  H04L61/00 ,  H04L67/00 ,  H04L67/10 ,  H04L67/1004 ,  H04L67/1008 ,  H04L67/1012 ,  H04L67/1014 ,  H04L67/1029 ,  H04L67/1034 ,  H04L67/1097 ,  H04L67/51 ,  H04Q1/04 ,  H04W4/02 ,  H04W4/80 ,  H05K1/02 ,  H05K1/18 ,  H05K5/02 ,  H05K7/20 ,  H05K13/04

CPC classification number: H04L43/08 ,  G02B6/3882 ,  G02B6/3893 ,  G02B6/3897 ,  G02B6/4292 ,  G02B6/4452 ,  G06F1/183 ,  G06F1/20 ,  G06F3/0613 ,  G06F3/0625 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0655 ,  G06F3/0664 ,  G06F3/0665 ,  G06F3/0673 ,  G06F3/0679 ,  G06F3/0683 ,  G06F3/0688 ,  G06F3/0689 ,  G06F8/65 ,  G06F9/30036 ,  G06F9/4401 ,  G06F9/544 ,  G06F12/109 ,  G06F12/1408 ,  G06F13/1668 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/409 ,  G06F15/161 ,  G06F16/9014 ,  G08C17/02 ,  G11C5/02 ,  G11C7/1072 ,  G11C11/56 ,  G11C14/0009 ,  H03M7/3086 ,  H03M7/4056 ,  H03M7/4081 ,  H04B10/25891 ,  H04L41/145 ,  H04L43/0817 ,  H04L43/0876 ,  H04L43/0894 ,  H04L49/00 ,  H04L49/25 ,  H04L49/357 ,  H04L49/45 ,  H04L67/02 ,  H04L67/306 ,  H04L69/04 ,  H04L69/329 ,  H04Q11/0003 ,  H05K7/1442 ,  B25J15/0014 ,  B65G1/0492 ,  G05D23/1921 ,  G05D23/2039 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0616 ,  G06F3/0619 ,  G06F3/0631 ,  G06F3/0638 ,  G06F3/0647 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/067 ,  G06F9/3887 ,  G06F9/5016 ,  G06F9/5044 ,  G06F9/505 ,  G06F9/5072 ,  G06F9/5077 ,  G06F11/141 ,  G06F11/3414 ,  G06F12/0862 ,  G06F12/0893 ,  G06F12/10 ,  G06F13/161 ,  G06F13/1694 ,  G06F13/42 ,  G06F13/4282 ,  G06F15/8061 ,  G06F2209/5019 ,  G06F2209/5022 ,  G06F2212/1008 ,  G06F2212/1024 ,  G06F2212/1041 ,  G06F2212/1044 ,  G06F2212/152 ,  G06F2212/202 ,  G06F2212/401 ,  G06F2212/402 ,  G06F2212/7207 ,  G06Q10/06 ,  G06Q10/06314 ,  G06Q10/087 ,  G06Q10/20 ,  G06Q50/04 ,  G07C5/008 ,  G08C2200/00 ,  G11C5/06 ,  H03M7/30 ,  H03M7/3084 ,  H03M7/40 ,  H03M7/4031 ,  H03M7/6005 ,  H03M7/6023 ,  H04B10/25 ,  H04J14/00 ,  H04L9/0643 ,  H04L9/14 ,  H04L9/3247 ,  H04L9/3263 ,  H04L12/2809 ,  H04L41/024 ,  H04L41/046 ,  H04L41/0813 ,  H04L41/082 ,  H04L41/0896 ,  H04L41/12 ,  H04L41/147 ,  H04L41/5019 ,  H04L43/065 ,  H04L43/16 ,  H04L45/02 ,  H04L45/52 ,  H04L47/24 ,  H04L47/38 ,  H04L47/765 ,  H04L47/782 ,  H04L47/805 ,  H04L47/82 ,  H04L47/823 ,  H04L49/15 ,  H04L49/555 ,  H04L61/00 ,  H04L67/10 ,  H04L67/1004 ,  H04L67/1008 ,  H04L67/1012 ,  H04L67/1014 ,  H04L67/1029 ,  H04L67/1034 ,  H04L67/1097 ,  H04L67/12 ,  H04L67/34 ,  H04L67/51 ,  H04Q1/04 ,  H04Q11/00 ,  H04Q11/0005 ,  H04Q2011/0037 ,  H04Q2011/0041 ,  H04Q2011/0052 ,  H04Q11/0062 ,  H04Q11/0071 ,  H04Q2011/0073 ,  H04Q2011/0079 ,  H04Q2011/0086 ,  H04Q2213/13523 ,  H04Q2213/13527 ,  H04W4/023 ,  H04W4/80 ,  H05K1/0203 ,  H05K1/181 ,  H05K5/0204 ,  H05K7/1418 ,  H05K7/1421 ,  H05K7/1422 ,  H05K7/1447 ,  H05K7/1461 ,  H05K7/1485 ,  H05K7/1487 ,  H05K7/1489 ,  H05K7/1491 ,  H05K7/1492 ,  H05K7/1498 ,  H05K7/2039 ,  H05K7/20709 ,  H05K7/20727 ,  H05K7/20736 ,  H05K7/20745 ,  H05K7/20836 ,  H05K13/0486 ,  H05K2201/066 ,  H05K2201/10121 ,  H05K2201/10159 ,  H05K2201/10189 ,  Y02D10/00 ,  Y02P90/30 ,  Y04S10/50 ,  Y04S10/52 ,  Y10S901/01

Abstract: Embodiments are generally directed apparatuses, methods, techniques and so forth determine an access level of operation based on an indication received via one or more network links from a pod management controller, and enable or disable a firmware update capability for a firmware device based on the access level of operation, the firmware update capability to change firmware for the firmware device. Embodiments may also include determining one or more configuration settings of a plurality of configuration settings to enable for configuration based on the access level of operation, and enable configuration of the one or more configuration settings.

公开(公告)号：US11703906B2

公开(公告)日：2023-07-18

申请号：US17520296

申请日：2021-11-05

Applicant: Intel Corporation

Inventor： Vasudevan Srinivasan ,  Krishnakanth V. Sistla ,  Corey D. Gough ,  Ian M. Steiner ,  Nikhil Gupta ,  Vivek Garg ,  Ankush Varma ,  Sujal A. Vora ,  David P. Lerner ,  Joseph M. Sullivan ,  Nagasubramanian Gurumoorthy ,  William J. Bowhill ,  Venkatesh Ramamurthy ,  Chris MacNamara ,  John J. Browne ,  Ripan Das

IPC: G06F1/08 ,  G06F1/3203 ,  G06F9/30 ,  G06F9/455 ,  G06F1/324

CPC classification number: G06F1/08 ,  G06F1/3203 ,  G06F1/324 ,  G06F9/30101 ,  G06F9/45558 ,  G06F2009/45591

Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.

公开(公告)号：US20230132432A1

公开(公告)日：2023-05-04

申请号：US18092163

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Katalin Klara Bartfai-Walcott ,  Arkadiusz Berent ,  Vasuki Chilukuri ,  Mark Baldwin ,  Vasudevan Srinivasan ,  Bartosz Gotowalski

IPC: G06F9/445 ,  G06F21/10 ,  H04L9/32 ,  G06F11/30

Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to provide device enhancements for software defined silicon implementations are disclosed. Example non-transitory computer readable medium includes instructions to cause one or more processors to at least generate a first stock keeping unit, associate the first stock keeping unit with a semiconductor device, the first stock keeping unit associated with a first set of features to be provided by the semiconductor device, command the semiconductor device to activate a feature not included in the first set of features to cause the semiconductor device to provide a second set of features, generate a second stock keeping unit for the semiconductor device, and associate the second stock keeping unit with the semiconductor device and the second set of features to be provided by the semiconductor device.

公开(公告)号：US20210012357A1

公开(公告)日：2021-01-14

申请号：US17033252

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Katalin Klara Bartfai-Walcott ,  Arkadiusz Berent ,  Vasuki Chilukuri ,  Mark Baldwin ,  Vasudevan Srinivasan ,  Justyna Chilczuk ,  Bartosz Gotowalski

IPC: G06Q30/00 ,  G06F21/73 ,  G06F21/10 ,  G06F21/72 ,  G06F21/75 ,  G06Q20/12

Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to protect against misuse of software defined silicon products are disclosed. Example semiconductor devices disclosed herein include circuitry configurable to provide one or more features. Disclosed example semiconductor devices also include a license processor determine whether first identification information associated with a license received via a network from an enterprise system corresponds to second identification information associated with at least one of the semiconductor device or a customer, and configure the circuitry to activate a first one of the one or more features specified in the license in response to the first identification information corresponding to the second identification information.

公开(公告)号：US09898066B2

公开(公告)日：2018-02-20

申请号：US14645330

申请日：2015-03-11

Applicant: Intel Corporation

Inventor： Eric Distefano ,  Guy M. Therien ,  Vasudevan Srinivasan ,  Tawfik Rahal-Arabi ,  Venkatesh Ramani ,  Ryan D. Wells ,  Stephen H. Gunther ,  Jeremy Shrall ,  Hames Hermerding, II

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/00 ,  G06F1/20

CPC classification number: G06F1/3234 ,  G06F1/206 ,  G06F1/26 ,  Y02D10/16

Abstract: A technique to change a thermal design power (TDP) value. In one embodiment, one or more environmental or user-driven changes may cause a processor's TDP value to be changed. Furthermore, in some embodiments a change in TDP may alter a turbo mode target frequency.

公开(公告)号：US20240296055A1

公开(公告)日：2024-09-05

申请号：US18647965

申请日：2024-04-26

Applicant: Intel Corporation

Inventor： Katalin Klara Bartfai-Walcott ,  Arkadiusz Berent ,  Vasuki Chilukuri ,  Mark Baldwin ,  Vasudevan Srinivasan ,  Bartosz Gotowalski

IPC: G06F9/445 ,  G06F11/30 ,  G06F21/10 ,  G06Q10/087 ,  G06Q30/04 ,  H04L9/32

CPC classification number: G06F9/44505 ,  G06F11/3058 ,  G06F21/105 ,  H04L9/3247 ,  H04L9/3268 ,  H04L9/3278 ,  G06F21/1075 ,  G06Q10/087 ,  G06Q30/04

Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to provide device enhancements for software defined silicon implementations are disclosed. Example non-transitory computer readable medium comprising instructions cause one or more processors to at least cause transmission of a message to a semiconductor device, the message to cause the semiconductor device to unlock a first feature of the semiconductor device and associate a soft stock keeping unit with the semiconductor device having at least the first feature unlocked.

公开(公告)号：US11886918B2

公开(公告)日：2024-01-30

申请号：US17717859

申请日：2022-04-11

Applicant: INTEL CORPORATION

Inventor： Ankush Varma ,  Nikhil Gupta ,  Vasudevan Srinivasan ,  Krishnakanth Sistla ,  Nilanjan Palit ,  Abhinav Karhu ,  Eugene Gorbatov ,  Eliezer Weissmann

IPC: G06F9/50 ,  G06F9/48 ,  G06F9/54 ,  G06F15/80

CPC classification number: G06F9/5027 ,  G06F9/4812 ,  G06F9/4881 ,  G06F9/542 ,  G06F15/8038

Abstract: An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of cores; one or more peripheral component interconnects to couple the plurality of cores to memory, and in response to a core configuration command to deactivate a core of the plurality of cores, a region within the memory is updated with an indication of deactivation of the core.

公开(公告)号：US11599368B2

公开(公告)日：2023-03-07

申请号：US17033267

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Katalin Klara Bartfai-Walcott ,  Arkadiusz Berent ,  Vasuki Chilukuri ,  Mark Baldwin ,  Vasudevan Srinivasan ,  Bartosz Gotowalski

IPC: G06F9/445 ,  G06F21/10 ,  H04L9/32 ,  G06F11/30 ,  G06Q10/08 ,  G06Q30/04 ,  G06Q10/087

Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to provide device enhancements for software defined silicon implementations are disclosed. Example apparatus disclosed herein include a request interface to receive a request for a timestamp. Disclosed example apparatus also include a property checker to determine a first value of an electrical property of a feature embedded in a silicon product, the feature having electrical properties that change over time. Disclosed example apparatus further include a relative time determiner to calculate a relative time between the request and a previous event based on the first value of the electrical property and a second value of the electrical property, the second value of the electrical property associated with the previous event.

公开(公告)号：US20220413720A1

公开(公告)日：2022-12-29

申请号：US17359334

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Adwait Purandare ,  Ian Steiner ,  Vasudevan Srinivasan ,  Ankush Varma ,  Nikhil Gupta ,  Stanley Chen

IPC: G06F3/06

Abstract: In an embodiment, a processor includes multiple processing engines and a power control unit. The power control unit is to receive a mapping of multiple virtual partitions to sets of the processing engines, and in response to a receipt of the mapping of multiple of virtual partitions: access a power limit table for the processor, and generate multiple virtual partition power limit tables based on the power limit table for the processor, where each virtual partition power limit table is associated with a different virtual partition. Other embodiments are described and claimed.

公开(公告)号：US11341248B2

公开(公告)日：2022-05-24

申请号：US16229496

申请日：2018-12-21

Applicant: Intel Corporation

Inventor： Haifeng Gong ,  Vasudevan Srinivasan ,  Antonio J. Hasbun Marin

IPC: G06F21/57 ,  G06F21/60 ,  H04L9/32

Abstract: A system includes a processor coupled to an integrated circuit. The processor includes a non-volatile memory to store instructions to perform a boot process. The boot process is discontinued to prevent unauthorized use of the processor if a value received from the integrated circuit in response to a first value sent to the integrated is not valid.