公开(公告)号：US20220230995A1

公开(公告)日：2022-07-21

申请号：US17714979

申请日：2022-04-06

Applicant: INTEL CORPORATION

Inventor： Zhijun Xu ,  Bin Liu ,  Yong She ,  Zhicheng Ding

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00

Abstract: An apparatus comprising: a die stack comprising at least one die pair, the at least one die pair having a first die over a second die, the first die and the second die both having a first surface and a second surface, the second surface of the first die over the first surface of the second die; and an adhesive film between the first die and the second die of the at least one die pair; wherein the adhesive film comprises an insulating layer and a conductive layer, the insulating layer adhering to the second surface of the first die and the conductive layer adhering to the first surface of the second die.

公开(公告)号：US20210280558A1

公开(公告)日：2021-09-09

申请号：US16326650

申请日：2016-09-22

Applicant: Intel Corporation

Inventor： Mao Guo ,  Hyoung Il Kim ,  Yong She ,  Sireesha Gogineni

IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: Apparatuses, systems and methods associated with integrated circuit (IC) package design are disclosed herein. In embodiments, an IC package may include a first die and a second die. The IC package may include a spacer located between the first die and the second die, the spacer includes glass , and a molding compound that at least partially encompasses the first die, the second die, and the spacer. Other embodiments may be described and/or claimed.

公开(公告)号：US20210265305A1

公开(公告)日：2021-08-26

申请号：US16467975

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Zhicheng Ding ,  Bin Liu ,  Yong She ,  Hyoung Il Kim

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/498 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56

Abstract: Electronic device package technology is disclosed. An electronic device package in accordance with the present disclosure can include an electronic component, a redistribution layer, and an interposer electrically coupling the redistribution layer and the electronic component. The interposer can have interconnect interfaces on a top side electrically coupled to the electronic component and interconnect interfaces on a bottom side electrically coupled to the redistribution layer. A density of the interconnect interfaces on the top side can be greater than a density of the interconnect interfaces on the bottom side. Associated systems and methods are also disclosed.

公开(公告)号：US20200051929A1

公开(公告)日：2020-02-13

申请号：US16492323

申请日：2017-03-10

Applicant: Intel Corporation

Inventor： Yong She ,  Bin Liu ,  Zhicheng Ding ,  Aiping Tan

IPC: H01L23/00 ,  H01L25/065 ,  G11C5/04 ,  H01L27/11524 ,  H01L27/1157

Abstract: A microelectronic device can include a polymer, a semiconductor, and a matching layer. The polymer can include a first coefficient of thermal expansion. The semiconductor can be coupled to the polymer layer. The matching layer can be adjacent the semiconductor, and the matching layer can include a second coefficient of thermal expansion that is about the same as the first coefficient of thermal expansion.

公开(公告)号：US10438916B2

公开(公告)日：2019-10-08

申请号：US16078579

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Yong She

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56

Abstract: Techniques and mechanisms for provide interconnection with integrated circuitry. In an embodiment, a packaged device includes a substrate and one or more integrated circuit (IC) dies. A first conductive pad is formed at a first side of a first IC die, and a second conductive pad is formed at a second side of the substrate or another IC die. Wire bonding couples a wire between the first conductive pad and the second conductive pad, wherein a distal end of the wire is bonded, via a bump, to an adjoining one of the first conductive pad and the second conductive pad. A harness of the bump, which is less than a hardness of the wire, mitigates damage to the adjoining pad that might otherwise occur as a result of wire bonding stresses. In another embodiment, the wire includes copper (Cu) and the bump includes gold (Au) or silver (Ag).

公开(公告)号：US20190273037A1

公开(公告)日：2019-09-05

申请号：US16349095

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Zhicheng Ding ,  Yong She ,  Bin Liu ,  Aiping Tan ,  Li Deng

IPC: H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00

Abstract: A system in package includes a memory-die stack in memory module that is stacked vertically with respect to a processor die. Each memory die in the memory-die stack includes a vertical bond wire that emerges from a matrix for connection. Some configurations include the vertical bond wire emerging orthogonally beginning from a bond-wire pad. The matrix encloses the memory-die stack, the spacer, and at least a portion of the processor die.

公开(公告)号：US20180096946A1

公开(公告)日：2018-04-05

申请号：US15282754

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： John G. Meyers ,  Hyoung Il Kim ,  Yong She

IPC: H01L23/544 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L21/027

CPC classification number: H01L23/544 ,  H01L21/0274 ,  H01L21/563 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06562

Abstract: Electronic device package technology is disclosed. In one example, an electronic device includes a plurality of dies stacked on a substrate and a reference die on the plurality of dies and having a fiducial marker that indicates a spatial position of the plurality of dies for alignment of an electronics assembly tool. The fiducial marker can comprise a physical alteration of the reference die, such as indicia that is sawed or laser/plasma/chemical etched. A transparent dielectric layer is disposed on the reference die such that the tool can locate the fiducial marker in three dimensional space through the transparent layer. The dielectric layer is etched corresponding to a photomask after a photoresist is disposed on the dielectric layer. The etched dielectric layer comprises at least one redistribution layer electrically coupled to the vertical wire interconnect structure to provide an ultra-thin package. A method of aligning an electronics assembly tool is disclosed.

公开(公告)号：US11848281B2

公开(公告)日：2023-12-19

申请号：US17391612

申请日：2021-08-02

Applicant: Intel Corporation

Inventor： Yong She ,  Bin Liu ,  Zhicheng Ding ,  Aiping Tan

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/498 ,  G11C5/04 ,  H10B41/35 ,  H10B43/35

CPC classification number: H01L23/562 ,  G11C5/04 ,  H01L24/29 ,  H01L25/0657 ,  H10B41/35 ,  H10B43/35 ,  H01L2924/1438 ,  H01L2924/3511

Abstract: A microelectronic device can include a polymer, a semiconductor, and a matching layer. The polymer can include a first coefficient of thermal expansion. The semiconductor can be coupled to the polymer layer. The matching layer can be adjacent the semiconductor, and the matching layer can include a second coefficient of thermal expansion that is about the same as the first coefficient of thermal expansion.

公开(公告)号：US11830848B2

公开(公告)日：2023-11-28

申请号：US16467975

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Zhicheng Ding ,  Bin Liu ,  Yong She ,  Hyoung Il Kim

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5383 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/0651 ,  H01L2225/06506 ,  H01L2225/06562

Abstract: Electronic device package technology is disclosed. An electronic device package in accordance with the present disclosure can include an electronic component, a redistribution layer, and an interposer electrically coupling the redistribution layer and the electronic component. The interposer can have interconnect interfaces on a top side electrically coupled to the electronic component and interconnect interfaces on a bottom side electrically coupled to the redistribution layer. A density of the interconnect interfaces on the top side can be greater than a density of the interconnect interfaces on the bottom side. Associated systems and methods are also disclosed.

公开(公告)号：US11538746B2

公开(公告)日：2022-12-27

申请号：US16349095

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Zhicheng Ding ,  Yong She ,  Bin Liu ,  Aiping Tan ,  Li Deng

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L23/31

Abstract: A system in package includes a memory-die stack in memory module that is stacked vertically with respect to a processor die. Each memory die in the memory-die stack includes a vertical bond wire that emerges from a matrix for connection. Some configurations include the vertical bond wire emerging orthogonally beginning from a bond-wire pad. The matrix encloses the memory-die stack, the spacer, and at least a portion of the processor die.