公开(公告)号：US11302671B2

公开(公告)日：2022-04-12

申请号：US16641221

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Zhijun Xu ,  Bin Liu ,  Yong She ,  Zhicheng Ding

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00

Abstract: An apparatus comprising: a die stack comprising at least one die pair, the at least one die pair having a first die over a second die, the first die and the second die both having a first surface and a second surface, the second surface of the first die over the first surface of the second die; and an adhesive film between the first die and the second die of the at least one die pair; wherein the adhesive film comprises an insulating layer and a conductive layer, the insulating layer adhering to the second surface of the first die and the conductive layer adhering to the first surface of the second die.

公开(公告)号：US10991679B2

公开(公告)日：2021-04-27

申请号：US17011598

申请日：2020-09-03

Applicant: Intel Corporation

Inventor： Zhicheng Ding ,  Bin Liu ,  Yong She ,  Aiping Tan ,  Li Deng

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L21/66 ,  H01L25/00 ,  H01L23/31

Abstract: A system in package includes a stair-stacked memory module that is stacked vertically with respect to a processor die. A spacer is used adjacent to the processor die to create a bridge for the stair-stacked memory module. Each memory die in the stair-stacked memory module includes a vertical bond wire that emerges from a matrix for connection. The matrix encloses the stair-stacked memory module and at least a portion of the processor die.

公开(公告)号：US20190229092A1

公开(公告)日：2019-07-25

申请号：US16326343

申请日：2016-09-29

Applicant: Intel Corporation

Inventor： Zhicheng Ding ,  Bin Liu ,  Yong She ,  Aiping Tan ,  Li Deng

IPC: H01L25/065 ,  H01L25/18 ,  H01L21/66 ,  H01L25/00 ,  G01R31/28

Abstract: A pre-packaged stair-stacked memory module is mounted on a board with at least one additional component. A stair-stacked memory module includes a plurality of memory dice that are stacked vertically with respect to a processor die. A spacer is used adjacent to the processor die to create a bridge for the stair-stacked memory module. Each memory die in the stair-stacked memory module includes a vertical bond wire that emerges from a matrix for connection. The matrix encloses the stair-stacked memory module and and at least a portion of the processor die. The matrix might also enclose the at least one additional component.

公开(公告)号：US20220230995A1

公开(公告)日：2022-07-21

申请号：US17714979

申请日：2022-04-06

Applicant: INTEL CORPORATION

Inventor： Zhijun Xu ,  Bin Liu ,  Yong She ,  Zhicheng Ding

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00

Abstract: An apparatus comprising: a die stack comprising at least one die pair, the at least one die pair having a first die over a second die, the first die and the second die both having a first surface and a second surface, the second surface of the first die over the first surface of the second die; and an adhesive film between the first die and the second die of the at least one die pair; wherein the adhesive film comprises an insulating layer and a conductive layer, the insulating layer adhering to the second surface of the first die and the conductive layer adhering to the first surface of the second die.

公开(公告)号：US20210265305A1

公开(公告)日：2021-08-26

申请号：US16467975

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Zhicheng Ding ,  Bin Liu ,  Yong She ,  Hyoung Il Kim

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/498 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56

Abstract: Electronic device package technology is disclosed. An electronic device package in accordance with the present disclosure can include an electronic component, a redistribution layer, and an interposer electrically coupling the redistribution layer and the electronic component. The interposer can have interconnect interfaces on a top side electrically coupled to the electronic component and interconnect interfaces on a bottom side electrically coupled to the redistribution layer. A density of the interconnect interfaces on the top side can be greater than a density of the interconnect interfaces on the bottom side. Associated systems and methods are also disclosed.

公开(公告)号：US11101254B2

公开(公告)日：2021-08-24

申请号：US15777810

申请日：2015-12-25

Applicant: Intel Corporation

Inventor： Zhicheng Ding ,  Bin Liu

IPC: H01L25/16 ,  H01L21/66 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00 ,  H01L25/065

Abstract: A system in package and method for making a system in package. A plurality of passive devices are coupled to an interposer. A molding compound envelopes the plurality of passive devices and defines a platform having a substantially planar surface. The interposer is coupled to a substrate. A plurality of integrated circuit dies are coupled in a stack to the planar surface.

公开(公告)号：US20200051929A1

公开(公告)日：2020-02-13

申请号：US16492323

申请日：2017-03-10

Applicant: Intel Corporation

Inventor： Yong She ,  Bin Liu ,  Zhicheng Ding ,  Aiping Tan

IPC: H01L23/00 ,  H01L25/065 ,  G11C5/04 ,  H01L27/11524 ,  H01L27/1157

Abstract: A microelectronic device can include a polymer, a semiconductor, and a matching layer. The polymer can include a first coefficient of thermal expansion. The semiconductor can be coupled to the polymer layer. The matching layer can be adjacent the semiconductor, and the matching layer can include a second coefficient of thermal expansion that is about the same as the first coefficient of thermal expansion.

公开(公告)号：US20190273037A1

公开(公告)日：2019-09-05

申请号：US16349095

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Zhicheng Ding ,  Yong She ,  Bin Liu ,  Aiping Tan ,  Li Deng

IPC: H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00

Abstract: A system in package includes a memory-die stack in memory module that is stacked vertically with respect to a processor die. Each memory die in the memory-die stack includes a vertical bond wire that emerges from a matrix for connection. Some configurations include the vertical bond wire emerging orthogonally beginning from a bond-wire pad. The matrix encloses the memory-die stack, the spacer, and at least a portion of the processor die.

公开(公告)号：US11848281B2

公开(公告)日：2023-12-19

申请号：US17391612

申请日：2021-08-02

Applicant: Intel Corporation

Inventor： Yong She ,  Bin Liu ,  Zhicheng Ding ,  Aiping Tan

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/498 ,  G11C5/04 ,  H10B41/35 ,  H10B43/35

CPC classification number: H01L23/562 ,  G11C5/04 ,  H01L24/29 ,  H01L25/0657 ,  H10B41/35 ,  H10B43/35 ,  H01L2924/1438 ,  H01L2924/3511

Abstract: A microelectronic device can include a polymer, a semiconductor, and a matching layer. The polymer can include a first coefficient of thermal expansion. The semiconductor can be coupled to the polymer layer. The matching layer can be adjacent the semiconductor, and the matching layer can include a second coefficient of thermal expansion that is about the same as the first coefficient of thermal expansion.

公开(公告)号：US11830848B2

公开(公告)日：2023-11-28

申请号：US16467975

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Zhicheng Ding ,  Bin Liu ,  Yong She ,  Hyoung Il Kim

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5383 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/0651 ,  H01L2225/06506 ,  H01L2225/06562

Abstract: Electronic device package technology is disclosed. An electronic device package in accordance with the present disclosure can include an electronic component, a redistribution layer, and an interposer electrically coupling the redistribution layer and the electronic component. The interposer can have interconnect interfaces on a top side electrically coupled to the electronic component and interconnect interfaces on a bottom side electrically coupled to the redistribution layer. A density of the interconnect interfaces on the top side can be greater than a density of the interconnect interfaces on the bottom side. Associated systems and methods are also disclosed.