公开(公告)号：US20170069591A1

公开(公告)日：2017-03-09

申请号：US15357553

申请日：2016-11-21

Applicant: Invensas Corporation

Inventor： Rajesh Katkar ,  Tu Tam Vu ,  Bongsub Lee ,  Kyong-Mo Bang ,  Xuan Li ,  Long Huynh ,  Gabriel Z. Guevara ,  Akash Agrawal ,  Willmar Subido ,  Laura Wills Mirkarimi

IPC: H01L23/00 ,  H01L25/065 ,  H01L21/78 ,  H01L25/10 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L24/49 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/48 ,  H01L24/85 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/4801 ,  H01L2224/48235 ,  H01L2224/484 ,  H01L2224/4845 ,  H01L2224/49171 ,  H01L2224/49173 ,  H01L2224/49177 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/85005 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/2064 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: An apparatus relates generally to a microelectronic package. In such an apparatus, a microelectronic die has a first surface, a second surface opposite the first surface, and a sidewall surface between the first and second surfaces. A plurality of wire bond wires with proximal ends thereof are coupled to either the first surface or the second surface of the microelectronic die with distal ends of the plurality of wire bond wires extending away from either the first surface or the second surface, respectively, of the microelectronic die. A portion of the plurality of wire bond wires extends outside a perimeter of the microelectronic die into a fan-out (“FO”) region. A molding material covers the first surface, the sidewall surface, and portions of the plurality of the wire bond wires from the first surface of the microelectronic die to an outer surface of the molding material.

Abstract translation: 一种装置一般涉及微电子封装。 在这种装置中，微电子管芯具有第一表面，与第一表面相对的第二表面和第一表面和第二表面之间的侧壁表面。 多个具有近端的引线接合线被耦合到微电子管芯的第一表面或第二表面，多个引线接合线的远端分别远离第一表面或第二表面 微电子模具。 多个引线接合线的一部分在微电子管芯的周边外延伸到扇出（“FO”）区域中。 成型材料覆盖第一表面，侧壁表面以及多个引线接合线从微电子管芯的第一表面到模制材料的外表面的部分。

公开(公告)号：US09543277B1

公开(公告)日：2017-01-10

申请号：US14830973

申请日：2015-08-20

Applicant: Invensas Corporation

Inventor： Bongsub Lee ,  Tu Tam Vu ,  Rajesh Katkar ,  Laura Wills Mirkarimi ,  Akash Agrawal ,  Kyong-Mo Bang ,  Gabriel Z. Guevara ,  Xuan Li ,  Long Huynh

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L24/03 ,  H01L24/06 ,  H01L24/43 ,  H01L24/46 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/49111 ,  H01L2224/49112 ,  H01L2224/49171 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/18165 ,  H01L2924/20751 ,  H01L2924/2075 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2224/05599

Abstract: A fan-out microelectronic package is provided in which bond wires electrically couple bond pads on a microelectronic element, e.g., a semiconductor chip which may have additional traces thereon, with contacts at a fan-out area of a dielectric element adjacent an edge surface of the chip. The bond wires mechanically decouple the microelectronic element from the fan-out area, which can make the electrical interconnections less prone to reliability issues due to effects of differential thermal expansion, such as caused by temperature excursions during initial package fabrication, bonding operations or thermal cycling. In addition, mechanical decoupling provided by the bond wires may also remedy other mechanical issues such as shock and possible delamination of package elements.

Abstract translation: 提供了一种扇出式微电子封装，其中，接合线将微电子元件（例如，可能在其上具有附加迹线的半导体芯片）上的接合焊盘电耦合，并且电介质元件的邻近边缘表面的电介质元件的扇出区域处的触点 芯片。 接合线将微电子元件与扇出区域机械地分离，这可以使得由于差分热膨胀的影响而导致电互连不容易产生可靠性问题，例如由初始封装制造，接合操作或热循环期间的温度漂移引起的 。 此外，由接合线提供的机械解耦也可以补救其他机械问题，例如冲击和包装元件的可能的分层。

公开(公告)号：US20170323867A1

公开(公告)日：2017-11-09

申请号：US15147807

申请日：2016-05-05

Applicant: Invensas Corporation

Inventor： Liang Wang ,  Bongsub Lee ,  Belgacem Haba ,  Sangil Lee

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L24/11 ,  H01L24/17 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/50 ,  H01L2224/11426 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16112 ,  H01L2224/16145 ,  H01L2224/27003 ,  H01L2224/2761 ,  H01L2224/27618 ,  H01L2224/2783 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/8385 ,  H01L2224/9211 ,  H01L2225/06513 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01079 ,  H01L2924/0615 ,  H01L2924/0635 ,  H01L2924/0645 ,  H01L2924/00

Abstract: A microelectronic assembly including an insulating layer having a plurality of nanoscale conductors disposed in a nanoscale pitch array therein and a pair of microelectronic elements is provided. The nanoscale conductors can form electrical interconnections between contacts of the microelectronic elements while the insulating layer can mechanically couple the microelectronic elements together.

公开(公告)号：US09502372B1

公开(公告)日：2016-11-22

申请号：US14701049

申请日：2015-04-30

Applicant: Invensas Corporation

Inventor： Rajesh Katkar ,  Tu Tam Vu ,  Bongsub Lee ,  Kyong-Mo Bang ,  Xuan Li ,  Long Huynh ,  Gabriel Z. Guevara ,  Akash Agrawal ,  Willmar Subido ,  Laura Wills Mirkarimi

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L24/49 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/48 ,  H01L24/85 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/4801 ,  H01L2224/48235 ,  H01L2224/484 ,  H01L2224/4845 ,  H01L2224/49171 ,  H01L2224/49173 ,  H01L2224/49177 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/85005 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/2064 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: An apparatus relates generally to a microelectronic package. In such an apparatus, a microelectronic die has a first surface, a second surface opposite the first surface, and a sidewall surface between the first and second surfaces. A plurality of wire bond wires with proximal ends thereof are coupled to either the first surface or the second surface of the microelectronic die with distal ends of the plurality of wire bond wires extending away from either the first surface or the second surface, respectively, of the microelectronic die. A portion of the plurality of wire bond wires extends outside a perimeter of the microelectronic die into a fan-out (“FO”) region. A molding material covers the first surface, the sidewall surface, and portions of the plurality of the wire bond wires from the first surface of the microelectronic die to an outer surface of the molding material.

Abstract translation: 一种装置一般涉及微电子封装。 在这种装置中，微电子管芯具有第一表面，与第一表面相对的第二表面和第一表面和第二表面之间的侧壁表面。 多个具有近端的引线接合线被耦合到微电子管芯的第一表面或第二表面，多个引线接合线的远端分别远离第一表面或第二表面 微电子模具。 多个引线接合线的一部分在微电子管芯的周边外延伸到扇出（“FO”）区域中。 成型材料覆盖第一表面，侧壁表面以及多个引线接合线从微电子管芯的第一表面到模制材料的外表面的部分。

公开(公告)号：US10008469B2

公开(公告)日：2018-06-26

申请号：US15357553

申请日：2016-11-21

Applicant: Invensas Corporation

Inventor： Rajesh Katkar ,  Tu Tam Vu ,  Bongsub Lee ,  Kyong-Mo Bang ,  Xuan Li ,  Long Huynh ,  Gabriel Z. Guevara ,  Akash Agrawal ,  Willmar Subido ,  Laura Wills Mirkarimi

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L21/56 ,  H01L21/78 ,  H01L23/538 ,  H01L25/10 ,  H01L25/00 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L24/49 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/48 ,  H01L24/85 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/4801 ,  H01L2224/48235 ,  H01L2224/484 ,  H01L2224/4845 ,  H01L2224/49171 ,  H01L2224/49173 ,  H01L2224/49177 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/85005 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/2064 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: An apparatus relates generally to a microelectronic package. In such an apparatus, a microelectronic die has a first surface, a second surface opposite the first surface, and a sidewall surface between the first and second surfaces. A plurality of wire bond wires with proximal ends thereof are coupled to either the first surface or the second surface of the microelectronic die with distal ends of the plurality of wire bond wires extending away from either the first surface or the second surface, respectively, of the microelectronic die. A portion of the plurality of wire bond wires extends outside a perimeter of the microelectronic die into a fan-out (“FO”) region. A molding material covers the first surface, the sidewall surface, and portions of the plurality of the wire bond wires from the first surface of the microelectronic die to an outer surface of the molding material.

公开(公告)号：US09847238B2

公开(公告)日：2017-12-19

申请号：US15443371

申请日：2017-02-27

Applicant: Invensas Corporation

Inventor： Xuan Li ,  Rajesh Katkar ,  Long Huynh ,  Laura Wills Mirkarimi ,  Bongsub Lee ,  Gabriel Z. Guevara ,  Tu Tam Vu ,  Kyong-Mo Bang ,  Akash Agrawal

IPC: H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L25/00 ,  H01L21/02 ,  H01L23/00 ,  H01L21/304 ,  H01L23/29 ,  H01L25/065

CPC classification number: H01L21/568 ,  H01L21/02118 ,  H01L21/304 ,  H01L21/4846 ,  H01L21/561 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/76838 ,  H01L21/76892 ,  H01L23/293 ,  H01L23/3135 ,  H01L23/4985 ,  H01L23/5384 ,  H01L24/09 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/19 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13006 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/16111 ,  H01L2224/16237 ,  H01L2224/27436 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/73203 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/8185 ,  H01L2224/81903 ,  H01L2224/81904 ,  H01L2224/8192 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2224/81 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Fan-out wafer-level packaging (WLP) using metal foil lamination is provided. An example wafer-level package incorporates a metal foil, such as copper (Cu), to relocate bonding pads in lieu of a conventional deposited or plated RDL. A polymer such as an epoxy layer adheres the metal foil to the package creating conductive contacts between the metal foil and metal pillars of a die. The metal foil may be patterned at different stages of a fabrication process. An example wafer-level package with metal foil provides relatively inexpensive electroplating-free traces that replace expensive RDL processes. Example techniques can reduce interfacial stress at fan-out areas to enhance package reliability, and enable smaller chips to be used. The metal foil provides improved fidelity of high frequency signals. The metal foil can be bonded to metallic pillar bumps before molding, resulting in less impact on the mold material.

公开(公告)号：US20170103957A1

公开(公告)日：2017-04-13

申请号：US14877205

申请日：2015-10-07

Applicant: Invensas Corporation

Inventor： Xuan Li ,  Rajesh Katkar ,  Long Huynh ,  Laura Wills Mirkarimi ,  Bongsub Lee ,  Gabriel Z. Guevara ,  Tu Tam Vu ,  Kyong-Mo Bang ,  Akash Agrawal

IPC: H01L23/00 ,  H01L21/683 ,  H01L23/29 ,  H01L21/56 ,  H01L21/304 ,  H01L23/538 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L21/568 ,  H01L21/02118 ,  H01L21/304 ,  H01L21/4846 ,  H01L21/561 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/76838 ,  H01L21/76892 ,  H01L23/293 ,  H01L23/3135 ,  H01L23/4985 ,  H01L23/5384 ,  H01L24/09 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/19 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13006 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/16111 ,  H01L2224/16237 ,  H01L2224/27436 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/73203 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/8185 ,  H01L2224/81903 ,  H01L2224/81904 ,  H01L2224/8192 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2224/81 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Fan-out wafer-level packaging (WLP) using metal foil lamination is provided. An example wafer-level package incorporates a metal foil, such as copper (Cu), to relocate bonding pads in lieu of a conventional deposited or plated RDL. A polymer such as an epoxy layer adheres the metal foil to the package creating conductive contacts between the metal foil and metal pillars of a die. The metal foil may be patterned at different stages of a fabrication process. An example wafer-level package with metal foil provides relatively inexpensive electroplating-free traces that replace expensive RDL processes. Example techniques can reduce interfacial stress at fan-out areas to enhance package reliability, and enable smaller chips to be used. The metal foil provides improved fidelity of high frequency signals. The metal foil can be bonded to metallic pillar bumps before molding, resulting in less impact on the mold material.

公开(公告)号：US20170040270A1

公开(公告)日：2017-02-09

申请号：US14819744

申请日：2015-08-06

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Guilian Gao ,  Bongsub Lee ,  Scott McGrath ,  Hong Shen ,  Charles G. Woychik ,  Arkalgud R. Sitaram ,  Akash Agrawal

IPC: H01L23/00 ,  H01L23/48 ,  H01L21/311

CPC classification number: H01L24/03 ,  H01L21/31144 ,  H01L21/486 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02126 ,  H01L2224/03009 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/10126 ,  H01L2224/13016 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A method of processing an interconnection element can include providing a substrate element having front and rear opposite surfaces and electrically conductive structure, a first dielectric layer overlying the front surface and a plurality of conductive contacts at a first surface of the first dielectric layer, and a second dielectric layer overlying the rear surface and having a conductive element at a second surface of the second dielectric layer. The method can also include removing a portion of the second dielectric layer so as to reduce the thickness of the portion, and to provide a raised portion of the second dielectric layer having a first thickness and a lowered portion having a second thickness. The first thickness can be greater than the second thickness. At least a portion of the conductive element can be recessed below a height of the first thickness of the second dielectric layer.

Abstract translation: 处理互连元件的方法可以包括提供具有前后相对表面和导电结构的衬底元件，覆盖前表面的第一电介质层和在第一介电层的第一表面处的多个导电触点，以及 第二电介质层覆盖在后表面上并且在第二介电层的第二表面处具有导电元件。 该方法还可以包括去除第二电介质层的一部分以减小该部分的厚度，并且提供具有第一厚度的第二介电层的凸起部分和具有第二厚度的下降部分。 第一厚度可以大于第二厚度。 导电元件的至少一部分可以凹陷到第二介电层的第一厚度的高度以下。

公开(公告)号：US10600761B2

公开(公告)日：2020-03-24

申请号：US16378921

申请日：2019-04-09

Applicant: Invensas Corporation

Inventor： Liang Wang ,  Bongsub Lee ,  Belgacem Haba ,  Sangil Lee

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: A microelectronic assembly including an insulating layer having a plurality of nanoscale conductors disposed in a nanoscale pitch array therein and a pair of microelectronic elements is provided. The nanoscale conductors can form electrical interconnections between contacts of the microelectronic elements while the insulating layer can mechanically couple the microelectronic elements together.

公开(公告)号：US10304803B2

公开(公告)日：2019-05-28

申请号：US15147807

申请日：2016-05-05

Applicant: Invensas Corporation

Inventor： Liang Wang ,  Bongsub Lee ,  Belgacem Haba ,  Sangil Lee

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: A microelectronic assembly including an insulating layer having a plurality of nanoscale conductors disposed in a nanoscale pitch array therein and a pair of microelectronic elements is provided. The nanoscale conductors can form electrical interconnections between contacts of the microelectronic elements while the insulating layer can mechanically couple the microelectronic elements together.