公开(公告)号：US10566310B2

公开(公告)日：2020-02-18

申请号：US15095629

申请日：2016-04-11

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Kyong-Mo Bang

IPC: H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L23/495 ,  H01L25/00

Abstract: A microelectronic package includes at least one microelectronic element having a front surface defining a plane, the plane of each microelectronic element parallel to the plane of any other microelectronic element. An encapsulation region overlying edge surfaces of each microelectronic element has first and second major surfaces substantially parallel to the plane of each microelectronic element and peripheral surfaces between the major surfaces. Wire bonds are electrically coupled with one or more first package contacts at the first major surface of the encapsulation region, each wire bond having a portion contacted and surrounded by the encapsulation region. Second package contacts at an interconnect surface being one or more of the second major surface and the peripheral surfaces include portions of the wire bonds at such surface, and/or electrically conductive structure electrically coupled with the wire bonds.

公开(公告)号：US20170069591A1

公开(公告)日：2017-03-09

申请号：US15357553

申请日：2016-11-21

Applicant: Invensas Corporation

Inventor： Rajesh Katkar ,  Tu Tam Vu ,  Bongsub Lee ,  Kyong-Mo Bang ,  Xuan Li ,  Long Huynh ,  Gabriel Z. Guevara ,  Akash Agrawal ,  Willmar Subido ,  Laura Wills Mirkarimi

IPC: H01L23/00 ,  H01L25/065 ,  H01L21/78 ,  H01L25/10 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L24/49 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/48 ,  H01L24/85 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/4801 ,  H01L2224/48235 ,  H01L2224/484 ,  H01L2224/4845 ,  H01L2224/49171 ,  H01L2224/49173 ,  H01L2224/49177 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/85005 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/2064 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: An apparatus relates generally to a microelectronic package. In such an apparatus, a microelectronic die has a first surface, a second surface opposite the first surface, and a sidewall surface between the first and second surfaces. A plurality of wire bond wires with proximal ends thereof are coupled to either the first surface or the second surface of the microelectronic die with distal ends of the plurality of wire bond wires extending away from either the first surface or the second surface, respectively, of the microelectronic die. A portion of the plurality of wire bond wires extends outside a perimeter of the microelectronic die into a fan-out (“FO”) region. A molding material covers the first surface, the sidewall surface, and portions of the plurality of the wire bond wires from the first surface of the microelectronic die to an outer surface of the molding material.

Abstract translation: 一种装置一般涉及微电子封装。 在这种装置中，微电子管芯具有第一表面，与第一表面相对的第二表面和第一表面和第二表面之间的侧壁表面。 多个具有近端的引线接合线被耦合到微电子管芯的第一表面或第二表面，多个引线接合线的远端分别远离第一表面或第二表面 微电子模具。 多个引线接合线的一部分在微电子管芯的周边外延伸到扇出（“FO”）区域中。 成型材料覆盖第一表面，侧壁表面以及多个引线接合线从微电子管芯的第一表面到模制材料的外表面的部分。

公开(公告)号：US09543277B1

公开(公告)日：2017-01-10

申请号：US14830973

申请日：2015-08-20

Applicant: Invensas Corporation

Inventor： Bongsub Lee ,  Tu Tam Vu ,  Rajesh Katkar ,  Laura Wills Mirkarimi ,  Akash Agrawal ,  Kyong-Mo Bang ,  Gabriel Z. Guevara ,  Xuan Li ,  Long Huynh

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L24/03 ,  H01L24/06 ,  H01L24/43 ,  H01L24/46 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/49111 ,  H01L2224/49112 ,  H01L2224/49171 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/18165 ,  H01L2924/20751 ,  H01L2924/2075 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2224/05599

Abstract: A fan-out microelectronic package is provided in which bond wires electrically couple bond pads on a microelectronic element, e.g., a semiconductor chip which may have additional traces thereon, with contacts at a fan-out area of a dielectric element adjacent an edge surface of the chip. The bond wires mechanically decouple the microelectronic element from the fan-out area, which can make the electrical interconnections less prone to reliability issues due to effects of differential thermal expansion, such as caused by temperature excursions during initial package fabrication, bonding operations or thermal cycling. In addition, mechanical decoupling provided by the bond wires may also remedy other mechanical issues such as shock and possible delamination of package elements.

Abstract translation: 提供了一种扇出式微电子封装，其中，接合线将微电子元件（例如，可能在其上具有附加迹线的半导体芯片）上的接合焊盘电耦合，并且电介质元件的邻近边缘表面的电介质元件的扇出区域处的触点 芯片。 接合线将微电子元件与扇出区域机械地分离，这可以使得由于差分热膨胀的影响而导致电互连不容易产生可靠性问题，例如由初始封装制造，接合操作或热循环期间的温度漂移引起的 。 此外，由接合线提供的机械解耦也可以补救其他机械问题，例如冲击和包装元件的可能的分层。

公开(公告)号：US09496242B2

公开(公告)日：2016-11-15

申请号：US14658763

申请日：2015-03-16

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Kyong-Mo Bang

IPC: H01L25/065 ,  H01L25/10 ,  B81C1/00 ,  H01L23/31 ,  H01L23/00 ,  H01L23/13 ,  H01L23/367

Abstract: A microelectronic assembly includes a first microelectronic package having a substrate with first and second opposed surfaces and substrate contacts thereon. The first package further includes first and second microelectronic elements, each having element contacts electrically connected with the substrate contacts and being spaced apart from one another on the first surface so as to provide an interconnect area of the first surface between the first and second microelectronic elements. A plurality of package terminals at the second surface are electrically interconnected with the substrate contacts for connecting the package with a component external thereto. A plurality of stack terminals are exposed at the first surface in the interconnect area for connecting the package with a component overlying the first surface of the substrate. The assembly further includes a second microelectronic package overlying the first microelectronic package and having terminals joined to the stack terminals of the first microelectronic package.

公开(公告)号：US09343398B2

公开(公告)日：2016-05-17

申请号：US14497825

申请日：2014-09-26

Applicant: Invensas Corporation

Inventor： Yong Chen ,  Zhuowen Sun ,  Kyong-Mo Bang

IPC: H01L23/498 ,  H05K1/02

CPC classification number: H01L23/49816 ,  H01L23/49822 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2924/0002 ,  H01L2924/15192 ,  H01L2924/181 ,  H05K1/0262 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09336 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A microelectronic package can include a substrate and a microelectronic element. The substrate can include terminals comprising at least first power terminals and other terminals in an area array at a surface of the substrate. The substrate can also include a power plane element electrically coupled to the first power terminals. The area array can have a peripheral edge and a continuous gap between the terminals extending inwardly from the peripheral edge in a direction parallel to the surface. The terminals on opposite sides of the gap can be spaced from one another by at least 1.5 times a minimum pitch of the terminals. The power plane element can extend within the gap from at least the peripheral edge at least to the first power terminals. Each first power terminal can be separated from the peripheral edge by two or more of the other terminals.

Abstract translation: 微电子封装可以包括衬底和微电子元件。 衬底可以包括在衬底的表面处的区域阵列中至少包括第一电源端子和其他端子的端子。 基板还可以包括电耦合到第一电源端子的功率平面元件。 区域阵列可以具有周边边缘和在平行于表面的方向上从周边边缘向内延伸的端子之间的连续间隙。 间隙的相对侧上的端子可以彼此间隔开至少1.5倍的端子的最小间距。 功率平面元件可以在间隙内从至少外围边缘至少延伸到第一电源端子。 每个第一电源端子可以通过两个或更多其它端子与外围边缘分离。

公开(公告)号：US10468380B2

公开(公告)日：2019-11-05

申请号：US15911868

申请日：2018-03-05

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Kyong-Mo Bang

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  B81C1/00 ,  H01L23/31 ,  H01L23/13 ,  H01L23/367

Abstract: A microelectronic assembly includes a first microelectronic package having a substrate with first and second opposed surfaces and substrate contacts thereon. The first package further includes first and second microelectronic elements, each having element contacts electrically connected with the substrate contacts and being spaced apart from one another on the first surface so as to provide an interconnect area of the first surface between the first and second microelectronic elements. A plurality of package terminals at the second surface are electrically interconnected with the substrate contacts for connecting the package with a component external thereto. A plurality of stack terminals are exposed at the first surface in the interconnect area for connecting the package with a component overlying the first surface of the substrate. The assembly further includes a second microelectronic package overlying the first microelectronic package and having terminals joined to the stack terminals of the first microelectronic package.

公开(公告)号：US10026467B2

公开(公告)日：2018-07-17

申请号：US15337323

申请日：2016-10-28

Applicant: Invensas Corporation

Inventor： Zhuowen Sun ,  Yong Chen ,  Kyong-Mo Bang

IPC: G11C5/06 ,  G11C11/408 ,  G11C8/18 ,  H01L25/065 ,  H01L25/18 ,  H01L23/64 ,  H01L23/31 ,  G11C11/409 ,  H01L23/02

CPC classification number: G11C11/4087 ,  G11C5/063 ,  G11C8/18 ,  G11C11/409 ,  H01L23/02 ,  H01L23/3128 ,  H01L23/64 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A microelectronic assembly can include an address bus comprising a plurality of signal conductors each passing sequentially through first, second, third, and fourth connection regions, and first and second microelectronic packages. The first microelectronic package can include first and second microelectronic elements, and the second microelectronic package can include third and fourth microelectronic elements. Each microelectronic element can be electrically coupled to the address bus via the respective connection region. An electrical characteristic between the first and second connection regions can be within a same tolerance of the electrical characteristic between the second and third connection regions.

公开(公告)号：US20170170031A1

公开(公告)日：2017-06-15

申请号：US15443371

申请日：2017-02-27

Applicant: Invensas Corporation

Inventor： Xuan Li ,  Rajesh Katkar ,  Long Huynh ,  Laura Wills Mirkarimi ,  Bongsub Lee ,  Gabriel Z. Guevara ,  Tu Tam Vu ,  Kyong-Mo Bang ,  Akash Agrawal

IPC: H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L25/00 ,  H01L21/304 ,  H01L23/29 ,  H01L25/065 ,  H01L21/02 ,  H01L23/00

CPC classification number: H01L21/568 ,  H01L21/02118 ,  H01L21/304 ,  H01L21/4846 ,  H01L21/561 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/76838 ,  H01L21/76892 ,  H01L23/293 ,  H01L23/3135 ,  H01L23/4985 ,  H01L23/5384 ,  H01L24/09 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/19 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13006 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/16111 ,  H01L2224/16237 ,  H01L2224/27436 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/73203 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/8185 ,  H01L2224/81903 ,  H01L2224/81904 ,  H01L2224/8192 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2224/81 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Fan-out wafer-level packaging (WLP) using metal foil lamination is provided. An example wafer-level package incorporates a metal foil, such as copper (Cu), to relocate bonding pads in lieu of a conventional deposited or plated RDL. A polymer such as an epoxy layer adheres the metal foil to the package creating conductive contacts between the metal foil and metal pillars of a die. The metal foil may be patterned at different stages of a fabrication process. An example wafer-level package with metal foil provides relatively inexpensive electroplating-free traces that replace expensive RDL processes. Example techniques can reduce interfacial stress at fan-out areas to enhance package reliability, and enable smaller chips to be used. The metal foil provides improved fidelity of high frequency signals. The metal foil can be bonded to metallic pillar bumps before molding, resulting in less impact on the mold material.

公开(公告)号：US09484080B1

公开(公告)日：2016-11-01

申请号：US14935705

申请日：2015-11-09

Applicant: Invensas Corporation

Inventor： Zhuowen Sun ,  Yong Chen ,  Kyong-Mo Bang

IPC: G11C5/06 ,  G11C11/408 ,  G11C8/18 ,  G11C11/409 ,  H01L25/065 ,  H01L25/18 ,  H01L23/02 ,  H01L23/64

CPC classification number: G11C11/4087 ,  G11C5/063 ,  G11C8/18 ,  G11C11/409 ,  H01L23/02 ,  H01L23/3128 ,  H01L23/64 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A microelectronic assembly can include an address bus comprising a plurality of signal conductors each passing sequentially through first, second, third, and fourth connection regions, and first and second microelectronic packages. The first microelectronic package can include first and second microelectronic elements, and the second microelectronic package can include third and fourth microelectronic elements. Each microelectronic element can be electrically coupled to the address bus via the respective connection region. An electrical characteristic between the first and second connection regions can be within a same tolerance of the electrical characteristic between the second and third connection regions.

Abstract translation: 微电子组件可以包括地址总线，其包括多个信号导体，每个信号导体顺序地通过第一，第二，第三和第四连接区域，以及第一和第二微电子封装。 第一微电子封装可以包括第一和第二微电子元件，并且第二微电子封装可以包括第三和第四微电子元件。 每个微电子元件可以经由相应的连接区域电耦合到地址总线。 第一和第二连接区域之间的电特性可以在第二和第三连接区域之间的电特性的相同公差内。

公开(公告)号：US09425167B2

公开(公告)日：2016-08-23

申请号：US14545019

申请日：2015-03-16

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Kyong-Mo Bang

IPC: H01L25/065 ,  H01L25/10 ,  B81C1/00 ,  H01L23/31 ,  H01L23/00 ,  H01L23/13 ,  H01L23/367

CPC classification number: H01L25/0655 ,  B81C1/00301 ,  H01L23/13 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/367 ,  H01L24/13 ,  H01L24/16 ,  H01L24/20 ,  H01L24/48 ,  H01L24/49 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/221 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48228 ,  H01L2224/4824 ,  H01L2224/49109 ,  H01L2224/4911 ,  H01L2224/96 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161 ,  H01L2924/18165 ,  H01L2924/19107 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A microelectronic assembly includes a first microelectronic package having a substrate with first and second opposed surfaces and substrate contacts thereon. The first package further includes first and second microelectronic elements, each having element contacts electrically connected with the substrate contacts and being spaced apart from one another on the first surface so as to provide an interconnect area of the first surface between the first and second microelectronic elements. A plurality of package terminals at the second surface are electrically interconnected with the substrate contacts for connecting the package with a component external thereto. A plurality of stack terminals are exposed at the first surface in the interconnect area for connecting the package with a component overlying the first surface of the substrate. The assembly further includes a second microelectronic package overlying the first microelectronic package and having terminals joined to the stack terminals of the first microelectronic package.