公开(公告)号：US10276722B2

公开(公告)日：2019-04-30

申请号：US15468042

申请日：2017-03-23

Applicant: JOLED INC.

Inventor： Toshiaki Yoshitani ,  Shinichi Ushikura

IPC: H01L29/786 ,  H01L29/49 ,  H01L29/51 ,  H01L27/12 ,  H01L27/32

Abstract: A thin film transistor includes an oxide semiconductor layer including a channel region, and a source region and a drain region having a resistivity lower than that of the channel region; a gate insulating layer disposed on the channel region of the oxide semiconductor layer; a gate electrode disposed on the gate insulating layer; and an aluminum oxide layer covering the lateral surface of the gate insulating layer, and the source region and the drain region, wherein the gate insulating layer has a multi-layer structure including a first insulating layer and a second insulating layer, and the first insulating layer contains silicon oxide as a main component, and is disposed on and in contact with the channel region.

公开(公告)号：US09202928B2

公开(公告)日：2015-12-01

申请号：US14480958

申请日：2014-09-09

Applicant: JOLED INC.

Inventor： Hiroshi Hayashi ,  Tomoaki Izumi ,  Mami Nonoguchi ,  Toshiaki Yoshitani

IPC: H01L21/26 ,  H01L29/786 ,  H01L21/02

CPC classification number: H01L29/78693 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/02664 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78696

Abstract: A thin film semiconductor device comprises a substrate, a gate electrode disposed above the substrate, an oxide semiconductor layer disposed above the substrate so as to oppose the gate electrode, a channel protective layer disposed on the oxide semiconductor layer, and a source electrode and a drain electrode each connected to the oxide semiconductor layer. The density of states DOS [eV−1cm−3] of oxygen defects in the oxide semiconductor layer satisfies the following relationship: DOS≦1.710×1017×(Ec−E)2−6.468×1017×(Ec−E)+6.113×1017 provided that 2.0 eV≦Ec−E≦2.7 eV where Ec [eV] is an energy level of a conduction band edge of the oxide semiconductor layer and E [eV] is a predetermined energy level of the oxide semiconductor layer.

Abstract translation: 薄膜半导体器件包括衬底，设置在衬底上方的栅极电极，设置在衬底上方以与栅电极相对的氧化物半导体层，设置在氧化物半导体层上的沟道保护层，以及源电极和 漏电极各自连接到氧化物半导体层。 氧化物半导体层中氧缺陷的状态密度DOS [eV-1cm-3]满足以下关系：DOS＆nlE; 1.710×1017×（Ec-E）2-6.468×1017×（Ec-E）+ 6.113× 101e，其中Ec [eV]是氧化物半导体层的导带边缘的能级，E [eV]是氧化物半导体层的预定能级。

公开(公告)号：US10249761B2

公开(公告)日：2019-04-02

申请号：US15800604

申请日：2017-11-01

Applicant: JOLED INC.

Inventor： Toshiaki Yoshitani ,  Hiroshi Hayashi ,  Ryo Koshiishi

IPC: H01L29/786 ,  H01L27/32

Abstract: A thin-film transistor (TFT) substrate is provided which includes: a substrate; a TFT disposed above the substrate; and a capacitor disposed above the substrate and electrically connected with the TFT, wherein the capacitor includes: a lower electrode layer disposed above the substrate and including an electrically conductive material as a main component; an upper electrode layer disposed above and opposed to the lower electrode layer and including, as a main component, an oxide semiconductor material to which electrical conductivity is given; and a capacitor insulating layer disposed between the lower electrode layer and the upper electrode layer. An extension extending outward from at least a portion of the outer edge of the lower electrode layer in plan view is provided to the lower electrode layer. In plan view, the upper electrode layer covers the lower electrode layer except the extension.

公开(公告)号：US09508866B1

公开(公告)日：2016-11-29

申请号：US14902048

申请日：2014-06-20

Applicant: JOLED INC.

Inventor： Yuji Kishida ,  Toshiaki Yoshitani

IPC: H01L27/14 ,  H01L29/786 ,  H01L29/423 ,  H01L29/417 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L29/78693 ,  H01L27/1225 ,  H01L29/41733 ,  H01L29/42356 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin-film transistor includes: a gate electrode; a channel layer not adjacent to the gate electrode; a channel protection layer exposing portion of the channel layer; a source electrode contacting the channel layer at portion of an exposed portion of the channel layer; and a drain electrode contacting the channel layer at portion of the exposed portion, in respective order. The channel layer includes oxide semiconductor. Surface of the channel protection layer includes upper surface and side surface extending from the upper surface to the exposed portion. The drain electrode has: a rising portion extending from above the exposed region to the channel layer along the side surface; and an upper surface covering portion continuous with the rising portion and extending onto portion of the upper surface. The upper surface covering portion has a facing portion facing a channel region and being 2.5 μm or less in channel length direction.

Abstract translation: 薄膜晶体管包括：栅电极; 与栅电极不相邻的沟道层; 通道层保护层暴露部分; 源电极在沟道层的暴露部分的部分处与沟道层接触; 以及在暴露部分的部分处以相应顺序与沟道层接触的漏电极。 沟道层包括氧化物半导体。 通道保护层的表面包括从上表面延伸到暴露部分的上表面和侧表面。 漏电极具有：沿着侧表面从暴露区域上方延伸到沟道层的上升部分; 以及与上升部连续并延伸到上表面的一部分的上表面覆盖部。 上表面覆盖部具有面向沟道区域的面对部，沟道长度方向为2.5μm以下。

公开(公告)号：US10431603B2

公开(公告)日：2019-10-01

申请号：US15863009

申请日：2018-01-05

Applicant: JOLED INC.

Inventor： Hiroshi Hayashi ,  Tokuaki Kuniyoshi ,  Yasuhiro Terai ,  Eri Matsuo ,  Toshiaki Yoshitani ,  Naoki Asano

IPC: H01L27/12 ,  H01L29/786 ,  H01L21/027 ,  H01L21/768 ,  H01L29/66 ,  H01L29/417

Abstract: A semiconductor device includes a substrate, a first wiring line, a semiconductor film, a second wiring line, and an insulating film. The substrate includes first, second, and third regions provided adjacently in this order in a predetermined direction. The first wiring line is provided on the substrate and provided in each of the first, second, and third regions. The semiconductor film has a low-resistance region in at least a portion thereof. The semiconductor film is provided between the first wiring line and the substrate in the first region, and is in contact with the first wiring line in the second region. The second wiring line is provided at a position closer to the substrate than the semiconductor film, and is in contact with the first wiring line in the third region. The insulating film is provided between the first wiring line and the semiconductor film in the first region.

公开(公告)号：US09741588B2

公开(公告)日：2017-08-22

申请号：US14580896

申请日：2014-12-23

Applicant: JOLED INC.

Inventor： Yuji Kishida ,  Toshiaki Yoshitani

IPC: H01L21/477 ,  H01L29/786 ,  H01L29/66 ,  H01L27/12

CPC classification number: H01L21/477 ,  H01L27/1225 ,  H01L27/1248 ,  H01L29/66969 ,  H01L29/78636 ,  H01L29/78693

Abstract: A method of manufacturing a thin-film transistor substrate which includes a thin-film transistor includes: forming a planarization layer comprising polyimide material above the thin-film transistor; and heating the thin-film transistor at a temperature of 240° C. or lower after the planarization layer is formed.