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    STUD BUMPED PRINTED CIRCUIT ASSEMBLY
    1.
    发明申请
    STUD BUMPED PRINTED CIRCUIT ASSEMBLY 有权

    公开(公告)号：US20230041747A1

    公开(公告)日：2023-02-09

    申请号：US17757003

    申请日：2020-11-25

    Applicant: James Rathburn

    Inventor： James Rathburn

    IPC: H05K1/02 ,  H05K3/46 ,  H05K3/40

    Abstract: A circuit board having a plurality of conductive layers including a first conductive layer and a second conductive layer is provided. The circuit board includes a plurality of non-conductive layers in-between respective conductive layers of the plurality of conductive layers. The plurality of non-conductive layers include at least a first non-conductive layer disposed between the first conductive layer and the second conductive layer. At least one collapsed stud bump extends at least partially through the first non-conductive layer to electrically couple the first conductive layer to the second conductive layer.

    Electrical interconnect IC device socket
    2.
    发明授权
    Electrical interconnect IC device socket 有权
    电气互连IC器件插座

    公开(公告)号：US09320133B2

    公开(公告)日：2016-04-19

    申请号：US13880461

    申请日：2011-12-05

    Applicant: James Rathburn

    Inventor： James Rathburn

    IPC: H05K1/02 ,  H01R43/02 ,  H05K3/40 ,  H05K1/14 ,  H05K3/34

    CPC classification number: H05K1/0228 ,  H01R43/0256 ,  H05K1/0296 ,  H05K1/141 ,  H05K3/3436 ,  H05K3/3484 ,  H05K3/40 ,  H05K3/4046 ,  H05K2201/10378 ,  H05K2203/041 ,  Y10T29/49147

    Abstract: A surface mount electrical interconnect is disclosed that provides an interface between a PCB and solder balls of a BGA device. The electrical interconnect includes a socket substrate and a plurality of electrically conductive contact members. The socket substrate has a first layer with a plurality of openings configured to receive solder balls of the BGA device and has a second layer with a plurality of slots defined therethrough that correspond to the plurality of openings. The contact members may be disposed in the openings in the first layer and through the plurality of slots of the second layer of the socket substrate. The contact members can be configured to engage a top portion, a center diameter, and a lower portion of the solder ball of the BGA device. Each contact member electrically couples a solder ball on the BGA device to the PCB.

    Abstract translation: 公开了一种表面贴装电互连，其提供了PCB与BGA器件的焊球之间的界面。 电互连包括插座衬底和多个导电接触构件。 插座衬底具有第一层，其具有多个开口，其被配置为接收BGA器件的焊球，并且具有第二层，其中限定了多个槽，其对应于多个开口。 接触构件可以设置在第一层中的开口中并且穿过插座衬底的第二层的多个槽中。 接触构件可以构造成接合BGA装置的焊球的顶部，中心直径和下部。 每个接触构件将BGA器件上的焊球电耦合到PCB。

    High performance electrical circuit structure
    3.
    发明授权
    High performance electrical circuit structure 有权
    高性能电路结构

    公开(公告)号：US09232654B2

    公开(公告)日：2016-01-05

    申请号：US13879783

    申请日：2011-10-18

    Applicant: James Rathburn

    Inventor： James Rathburn

    IPC: H05K1/00 ,  H05K1/18 ,  H01L23/538 ,  H05K3/32 ,  H05K3/40 ,  H05K3/46 ,  H05K1/11 ,  H05K1/16 ,  H05K3/12 ,  H05K3/30 ,  H01L23/498 ,  H05K1/02

    CPC classification number: H05K1/18 ,  H01L23/49811 ,  H01L23/5383 ,  H01L2224/16 ,  H01L2924/09701 ,  H01L2924/12044 ,  H05K1/0274 ,  H05K1/111 ,  H05K1/115 ,  H05K1/16 ,  H05K3/1291 ,  H05K3/30 ,  H05K3/325 ,  H05K3/4007 ,  H05K3/4664 ,  H05K2201/0133 ,  Y10T29/49155

    Abstract: A high performance electrical interconnect adapted to provide an interface between terminals on first and second circuit members. The electrical interconnect includes a first circuitry layer with a first surface and a second surface having a plurality of contact pads adapted to electrically coupled with the terminals on the first circuit member. At least one dielectric layer is printed on the first surface of the first circuitry layer. The dielectric layer includes a plurality recesses. A conductive material is deposited in at least a portion of the recesses to create circuit geometry electrically coupled with the first circuitry layer. A second circuitry layer includes a first surface a plurality of contact pads adapted to electrically couple with the terminals on the second circuit member and a second surface attached to the dielectric layers. The circuit geometry electrically couples the first circuitry layer to the second circuitry layer.

    Abstract translation: 一种适用于在第一和第二电路构件上的端子之间提供接口的高性能电互连。 电互连包括具有第一表面的第一电路层和具有适于与第一电路构件上的端子电耦合的多个接触焊盘的第二表面。 至少一个电介质层被印刷在第一电路层的第一表面上。 电介质层包括多个凹部。 导电材料沉积在凹陷的至少一部分中以产生与第一电路层电耦合的电路几何形状。 第二电路层包括第一表面，多个接触焊盘，其适于与第二电路部件上的端子电耦合，以及附接到电介质层的第二表面。 电路几何电耦合第一电路层到第二电路层。

    Singulated semiconductor device separable electrical interconnect
    5.
    发明授权
    Singulated semiconductor device separable electrical interconnect 有权
    单片半导体器件可分离电气互连

    公开(公告)号：US08984748B2

    公开(公告)日：2015-03-24

    申请号：US13319228

    申请日：2010-06-28

    Applicant: James Rathburn

    Inventor： James Rathburn

    IPC: H05K3/32 ,  G01R3/00 ,  G01R1/04 ,  G01R1/073

    CPC classification number: G01R3/00 ,  G01R1/0491 ,  G01R1/0735 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49169 ,  Y10T29/49204 ,  Y10T29/49222

    Abstract: A socket assembly that forms a solderless electrical interconnection between terminals on a singulated integrated circuit device and another circuit member. The socket housing has an opening adapted to receive the singulated integrated circuit device. The compliant printed circuit is positioned relative to the socket housing to electrically couple with the terminals on a singulated integrated circuit device located in the opening. The compliant printed circuit includes a dielectric base layer printed onto a surface of a fixture, while leaving cavities in the surface of the fixture exposed. A plurality of contact members are formed in the plurality of cavities in the fixture and coupled to the dielectric base layer. The contact members are exposed wherein the compliant printed circuit is removed from the fixture. At least one dielectric layer with recesses corresponding to a target circuit geometry is printed on the dielectric base layer. A conductive material is deposited in at least a portion of the recesses to form conductive traces electrically coupling the contact members to the other circuit member.

    Abstract translation: 插座组件，其在单个集成电路器件和另一个电路部件之间形成端子之间的无焊接电气互连。 插座壳体具有适于容纳单个集成电路装置的开口。 顺应印刷电路相对于插座壳体定位，以在位于开口中的单个集成电路装置上与端子电耦合。 柔性印刷电路包括印刷在固定装置表面上的电介质基层，同时在固定装置表面露出空腔。 多个接触构件形成在固定装置中的多个空腔中，并与电介质基底层耦合。 接触构件被暴露，其中柔性印刷电路从固定装置移除。 具有对应于目标电路几何形状的凹部的至少一个电介质层被印刷在电介质基底层上。 导电材料沉积在凹陷的至少一部分中以形成将接触构件电耦合到另一个电路构件的导电迹线。

    Compliant conductive nano-particle electrical interconnect
    7.
    发明授权
    Compliant conductive nano-particle electrical interconnect 有权
    符合导电纳米颗粒电气互连

    公开(公告)号：US08525346B2

    公开(公告)日：2013-09-03

    申请号：US13448914

    申请日：2012-04-17

    Applicant: James Rathburn

    Inventor： James Rathburn

    IPC: H01L23/48

    CPC classification number: H01L23/48 ,  B82Y10/00 ,  H01R23/722 ,  H05K1/0231 ,  H05K1/113 ,  H05K1/141 ,  H05K3/32 ,  H05K3/3436 ,  H05K3/4038 ,  H05K3/4069 ,  H05K7/1069 ,  H05K7/1092 ,  H05K2201/049 ,  Y10T29/4913 ,  Y10T29/49147

    Abstract: An electrical interconnect providing an interconnect between contacts on an IC device and contact pads on a printed circuit board (PCB). The electrical interconnect includes a substrate with a plurality of through holes extending from a first surface to a second surface. A resilient material is located in the through holes. The resilient material includes an opening extending from the first surface to the second surface. A plurality of discrete, free-flowing conductive nano-particles are located in the openings of the resilient material. The conductive particles are substantially free of non-conductive materials. A plurality of first contact members are located in the through holes adjacent the first surface and a plurality of second contact members are located in the through holes adjacent the second surface. The first and second contact members are electrically coupled to the nano-particles.

    Abstract translation: 提供IC器件上的触点与印刷电路板（PCB）上的接触焊盘之间的互连的电互连。 电互连包括具有从第一表面延伸到第二表面的多个通孔的基底。 弹性材料位于通孔中。 弹性材料包括从第一表面延伸到第二表面的开口。 多个离散的自由流动的导电纳米颗粒位于弹性材料的开口中。 导电颗粒基本上不含非导电材料。 多个第一接触构件位于邻近第一表面的通孔中，并且多个第二接触构件位于与第二表面相邻的通孔中。 第一和第二接触构件电耦合到纳米颗粒。

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