公开(公告)号：US20160149046A1

公开(公告)日：2016-05-26

申请号：US14944676

申请日：2015-11-18

Applicant: Japan Display Inc.

Inventor： Akihiro HANADA ,  Masayoshi Fuchi ,  Hajime Watakabe ,  Takashi Okada ,  Arichika Ishiba

IPC: H01L29/786 ,  H01L21/467 ,  H01L29/66 ,  H01L29/423 ,  H01L29/24

CPC classification number: H01L29/7869 ,  H01L21/467 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/78696

Abstract: According to one embodiment, a thin-film transistor and a method of manufacturing the thin-film transistor provided herein achieve enhanced reliability by preventing a disconnection in a gate insulating film at a position corresponding to an end surface of an oxide semiconductor layer. The oxide semiconductor layer includes a channel region, a source region, and a drain region. The channel region is placed between the source region and the drain region. The gate insulating film covers the oxide semiconductor layer in a range from at least a part of an upper surface to an end surface continuous with the upper surface of the oxide semiconductor layer. The oxide semiconductor layer is formed so as to have an oxygen concentration that becomes lower from a top side to a bottom side and the end surface is inclined so as to diverge from the top side to the bottom side.

Abstract translation: 根据一个实施例，本文提供的薄膜晶体管和制造薄膜晶体管的方法通过防止栅极绝缘膜在与氧化物半导体层的端面相对应的位置处的断开而实现增强的可靠性。 氧化物半导体层包括沟道区，源极区和漏极区。 沟道区域放置在源极区域和漏极区域之间。 栅极绝缘膜在从上表面至与氧化物半导体层的上表面连续的端面的至少一部分的范围内覆盖氧化物半导体层。 氧化物半导体层形成为具有从上侧到底侧变低的氧浓度，并且端面倾斜以从顶侧向底侧发散。

公开(公告)号：US12119407B2

公开(公告)日：2024-10-15

申请号：US18163045

申请日：2023-02-01

Applicant: Japan Display Inc.

Inventor： Masashi Tsubuku ,  Michiaki Sakamoto ,  Takashi Okada ,  Toshiki Kaneko ,  Tatsuya Toda

IPC: H01L29/786 ,  H01L29/417

CPC classification number: H01L29/7869 ,  H01L29/41733

Abstract: A semiconductor device includes a gate electrode on a substrate, a gate insulating film on the gate electrode, an oxide semiconductor film via the gate insulating film on the gate electrode, a source electrode and a drain electrode on the oxide semiconductor film, a protective film provided on the source electrode and the drain electrode; and a conductive layer provided on the protective film and overlapped on the oxide semiconductor layer. The protective film includes a first silicon oxide film and a first silicon nitride film. The first oxide film is in contact with the oxide semiconductor layer. The gate insulating film includes a second silicon nitride film and a second silicon oxide film. The second silicon oxide film is in contact with the oxide semiconductor layer. The oxide semiconductor layer has a first region located between the source electrode and the drain electrode in a plan view.

公开(公告)号：US20160149047A1

公开(公告)日：2016-05-26

申请号：US14944711

申请日：2015-11-18

Applicant: Japan Display Inc.

Inventor： Hajime Watakabe ,  Arichika Ishida ,  Takashi Okada ,  Masayoshi Fuchi ,  Akihiro Hanada

IPC: H01L29/786 ,  H01L23/00 ,  H01L21/385 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78606

Abstract: According to one embodiment, a thin-film transistor and a method of manufacturing the same achieve size reduction of the thin-film transistor while using an oxide semiconductor layer. The oxide semiconductor layer includes a channel region, a source region, and a drain region. A gate electrode is arranged at a position spaced from the channel region of the oxide semiconductor layer so as to face the channel region. A source electrode is electrically connected to the source region of the oxide semiconductor layer. A drain electrode is electrically connected to the drain region of the oxide semiconductor layer. An undercoat layer adjoins the source region and the drain region of the oxide semiconductor layer. A hydrogen blocking layer has a hydrogen concentration lower than that in the undercoat layer and separates the undercoat layer and the channel region of the oxide semiconductor layer.

Abstract translation: 根据一个实施例，薄膜晶体管及其制造方法在使用氧化物半导体层时实现薄膜晶体管的尺寸减小。 氧化物半导体层包括沟道区，源极区和漏极区。 栅电极配置在与氧化物半导体层的沟道区隔开的位置，以面对沟道区。 源极电极与氧化物半导体层的源极区电连接。 漏电极与氧化物半导体层的漏区电连接。 底涂层邻接氧化物半导体层的源极区和漏极区。 氢阻挡层的氢浓度低于底涂层中的氢浓度，并分离底涂层和氧化物半导体层的沟道区。

公开(公告)号：US10374096B2

公开(公告)日：2019-08-06

申请号：US15713077

申请日：2017-09-22

Applicant: Japan Display Inc.

Inventor： Miyuki Ishikawa ,  Arichika Ishida ,  Masayoshi Fuchi ,  Hajime Watakabe ,  Takashi Okada

IPC: H01L27/12 ,  H01L27/32 ,  H01L29/66 ,  H01L21/441 ,  H01L21/465 ,  H01L21/467 ,  H01L29/417 ,  H01L29/786

Abstract: According to one embodiment, a semiconductor device includes contact holes passing through a source region of a drain region of an interlayer insulating film and oxide semiconductor layer to reach an insulating substrate, wherein a source electrode and a drain electrode are formed inside the contact holes, respectively.

公开(公告)号：US10056495B2

公开(公告)日：2018-08-21

申请号：US15826820

申请日：2017-11-30

Applicant: Japan Display Inc.

Inventor： Takashi Okada

IPC: H01L29/786 ,  H01L21/266 ,  H01L27/12 ,  H01L29/66 ,  G09G3/3233 ,  G09G3/36 ,  H01L27/32 ,  G02F1/1368 ,  H01L21/265 ,  G02F1/1362 ,  G02F1/1343 ,  G02F1/1335

CPC classification number: H01L29/78621 ,  G02F1/133512 ,  G02F1/133514 ,  G02F1/13439 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/133519 ,  G02F2001/13685 ,  G02F2202/104 ,  G09G3/3233 ,  G09G3/3648 ,  G09G2300/0426 ,  G09G2300/0842 ,  G09G2300/0871 ,  G09G2320/0233 ,  H01L21/26513 ,  H01L21/266 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/127 ,  H01L27/1288 ,  H01L27/3244 ,  H01L27/3262 ,  H01L27/3276 ,  H01L29/66757 ,  H01L29/78675 ,  H01L29/78696 ,  H01L2227/323

Abstract: The purpose of the invention is to eliminate an abnormal current at an edge of a semiconductor layer in a thin film transistor. The invention is: A thin film transistor having a semiconductor layer comprising: a channel, a drain and a source are formed in the semiconductor layer, the channel has a channel length and a channel width, a LDD (Light Doped Drain) is formed between the channel and the drain or between the channel and the source, the LDD including a first LDD area, which is formed at a center of the LDD in the direction of the channel width, and a second LDD area, which is formed at an edge of the LDD in the direction of the channel width, wherein a width of the second LDD area in the channel length direction is bigger than a width of the first LDD area in the channel length direction.

公开(公告)号：US09911859B2

公开(公告)日：2018-03-06

申请号：US14944711

申请日：2015-11-18

Applicant: Japan Display Inc.

Inventor： Hajime Watakabe ,  Arichika Ishida ,  Takashi Okada ,  Masayoshi Fuchi ,  Akihiro Hanada

IPC: H01L29/10 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78606

Abstract: According to one embodiment, a thin-film transistor and a method of manufacturing the same achieve size reduction of the thin-film transistor while using an oxide semiconductor layer. The oxide semiconductor layer includes a channel region, a source region, and a drain region. A gate electrode is arranged at a position spaced from the channel region of the oxide semiconductor layer so as to face the channel region. A source electrode is electrically connected to the source region of the oxide semiconductor layer. A drain electrode is electrically connected to the drain region of the oxide semiconductor layer. An undercoat layer adjoins the source region and the drain region of the oxide semiconductor layer. A hydrogen blocking layer has a hydrogen concentration lower than that in the undercoat layer and separates the undercoat layer and the channel region of the oxide semiconductor layer.

公开(公告)号：US09831349B2

公开(公告)日：2017-11-28

申请号：US14725361

申请日：2015-05-29

Applicant: Japan Display Inc.

Inventor： Miyuki Ishikawa ,  Arichika Ishida ,  Masayoshi Fuchi ,  Hajime Watakabe ,  Takashi Okada

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/24 ,  H01L21/441 ,  H01L21/465 ,  H01L21/467 ,  H01L29/66 ,  H01L29/417 ,  H01L27/32

CPC classification number: H01L29/7869 ,  H01L21/441 ,  H01L21/465 ,  H01L21/467 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/3272 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78633 ,  H01L29/78696

Abstract: According to one embodiment, a semiconductor device includes contact holes passing through a source region of a drain region of an interlayer insulating film and oxide semiconductor layer to reach an insulating substrate, wherein a source electrode and a drain electrode are formed inside the contact holes, respectively.

公开(公告)号：US09285911B2

公开(公告)日：2016-03-15

申请号：US14152143

申请日：2014-01-10

Applicant: Japan Display Inc.

Inventor： Keiichi Saito ,  Hideyuki Takahashi ,  Takashi Nakamura ,  Satoru Tomita ,  Masahiro Tada ,  Hirotaka Hayashi ,  Takashi Okada ,  Yoshiro Aoki ,  Takanori Tsunashima

IPC: G06F3/045 ,  G06F3/041 ,  G06F3/044

Abstract: According to one embodiment, a display device includes a display pixel allocated at a matrix state in a display area, an image-reading device which detects strength of capacitive coupling by a dielectric material coming close to or making contact with the display area, and a control portion which controls each transistor of the image-reading device. The image-reading device includes a detection electrode which forms capacitance between the detection electrode and the dielectric material, a pre-charge gate line, a coupling pulse line, a readout gate line, a pre-charge line and a readout line. These lines supply a signal which drives the image-reading device. The image-reading device further includes a pre-charge transistor, an amplification transistor, a readout transistor, a compensation transistor, and a power-source switching transistor.

公开(公告)号：US12068399B2

公开(公告)日：2024-08-20

申请号：US17511633

申请日：2021-10-27

Applicant: Japan Display Inc.

Inventor： Akihiro Hanada ,  Takuo Kaitoh ,  Ryo Onodera ,  Takashi Okada ,  Tomoyuki Ito ,  Toshiki Kaneko

IPC: H01L29/66 ,  H01L21/385 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L29/66969 ,  H01L21/385 ,  H01L27/1225 ,  H01L29/7869

Abstract: According to one embodiment, a method for manufacturing a semiconductor device, includes forming a first insulating film which covers a gate electrode, forming an island-shaped oxide semiconductor in contact with the first insulating film, forming a second insulating film which covers the oxide semiconductor, forming a source electrode in contact with the oxide semiconductor, forming a drain electrode in contact with the oxide semiconductor, forming a third insulating film which covers the source electrode and the drain electrode and forming a channel region between the source electrode and the drain electrode by supplying oxygen from the third insulating film to the oxide semiconductor via the second insulating film.

公开(公告)号：US11594641B2

公开(公告)日：2023-02-28

申请号：US17111810

申请日：2020-12-04

Applicant: Japan Display Inc.

Inventor： Masashi Tsubuku ,  Michiaki Sakamoto ,  Takashi Okada ,  Toshiki Kaneko ,  Tatsuya Toda

IPC: H01L29/00 ,  H01L29/786 ,  H01L29/417

Abstract: A semiconductor device includes a gate electrode on a substrate, a gate insulating film on the gate electrode, an oxide semiconductor film via the gate insulating film on the gate electrode, a source electrode and a drain electrode on the oxide semiconductor film, a protective film provided on the source electrode and the drain electrode; and a conductive layer provided on the protective film and overlapped on the oxide semiconductor layer. The protective film includes a first silicon oxide film and a first silicon nitride film. The first oxide film is in contact with the oxide semiconductor layer. The gate insulating film includes a second silicon nitride film and a second silicon oxide film. The second silicon oxide film is in contact with the oxide semiconductor layer. The oxide semiconductor layer has a first region located between the source electrode and the drain electrode in a plan view.