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    Stationary massage device, system and methods for soft tissue strain release
    1.
    发明授权
    Stationary massage device, system and methods for soft tissue strain release 有权

    公开(公告)号：US10925794B2

    公开(公告)日：2021-02-23

    申请号：US15658413

    申请日：2017-07-25

    Applicant: Jason T. Su

    Inventor： Jason T. Su

    IPC: A61H1/00 ,  A61H1/02 ,  A61H7/00 ,  A61F7/00 ,  A61F7/03 ,  A61F7/08 ,  A61F7/02

    Abstract: A stationary massage device, system and corresponding methods are used for self-administrated or assisted soft tissue strain release (including trigger point therapy, strain-and-counterstrain therapy and neuromuscular release). The massage device comprises a body, wherein the body may include branches, each having flat surfaces, edges, ridges or corners. The surfaces, edges and ridges may be pushed along the myofilament direction of the soft tissues to produce pressing, rubbing, stretching and pulling actions on the soft tissues as stripping massages. The system can be configured to form different geometric shapes, and made of different materials of different firmness. The system can be further configured to perform unheated, or heated massages; and cooling treatments. In addition to being used alone, the system can be mounted on a piece of wall, a standing frame, furniture or a garment.

    Write-assist and power-down circuit for low power SRAM applications
    2.
    发明授权
    Write-assist and power-down circuit for low power SRAM applications 有权
    低功耗SRAM应用的写辅助和掉电电路

    公开(公告)号：US07835217B1

    公开(公告)日：2010-11-16

    申请号：US12547182

    申请日：2009-08-25

    Applicant: Jason T. Su ,  Karthik Swaminathan

    Inventor： Jason T. Su ,  Karthik Swaminathan

    IPC: G11C5/14

    CPC classification number: G11C7/22 ,  G11C11/419 ,  G11C2207/2227

    Abstract: Described herein are methods and apparatuses for write-assist voltage generation and power-down voltage scaling for static random access memory (SRAM) cells. According to various embodiments, an SRAM cell may include a local power supply voltage node for receiving a power supply voltage generated by a power supply voltage generator circuit, the generated power supply voltage being substantially equal to or less than a global power supply voltage provided to one or more transistors of the SRAM cell during a write-enable or power-down mode.

    Abstract translation: 这里描述了用于静态随机存取存储器（SRAM）单元的写辅助电压产生和掉电电压缩放的方法和装置。 根据各种实施例，SRAM单元可以包括用于接收由电源电压发生器电路产生的电源电压的本地电源电压节点，所产生的电源电压基本上等于或小于提供给 在写使能或掉电模式期间SRAM单元的一个或多个晶体管。

    Write-assist and power-down circuit for low power SRAM applications
    3.
    发明授权
    Write-assist and power-down circuit for low power SRAM applications 有权
    低功耗SRAM应用的写辅助和掉电电路

    公开(公告)号：US08310894B1

    公开(公告)日：2012-11-13

    申请号：US12946534

    申请日：2010-11-15

    Applicant: Jason T. Su ,  Karthik Swaminathan

    Inventor： Jason T. Su ,  Karthik Swaminathan

    IPC: G11C5/14

    CPC classification number: G11C7/22 ,  G11C11/419 ,  G11C2207/2227

    Abstract: Described herein are methods and apparatuses for write-assist voltage generation and power-down voltage scaling for static random access memory (SRAM) cells. According to various embodiments, an SRAM cell may include a local power supply voltage node for receiving a power supply voltage generated by a power supply voltage generator circuit, the generated power supply voltage being substantially equal to or less than a global power supply voltage provided to one or more transistors of the SRAM cell during a write-enable or power-down mode.

    Abstract translation: 这里描述了用于静态随机存取存储器（SRAM）单元的写辅助电压产生和掉电电压缩放的方法和装置。 根据各种实施例，SRAM单元可以包括用于接收由电源电压发生器电路产生的电源电压的本地电源电压节点，所产生的电源电压基本上等于或小于提供给 在写使能或掉电模式期间SRAM单元的一个或多个晶体管。

    Clock gater system
    5.
    发明授权
    Clock gater system 有权
    时钟门控系统

    公开(公告)号：US07639057B1

    公开(公告)日：2009-12-29

    申请号：US11949424

    申请日：2007-12-03

    Applicant: Jason T. Su

    Inventor： Jason T. Su

    IPC: G06F1/04 ,  H03K3/00

    CPC classification number: G06F1/10

    Abstract: A clock gater includes a first logic circuit that receives an enable signal and that includes first and second subcircuits. The clock gater also includes a latch that shares first and second nodes with the first logic circuit and that includes third and fourth subcircuits. The first logic circuit and the latch receive a clock signal that varies between first and second clock states. The first and third subcircuits pull the first and second nodes, respectively, to a common precharge voltage based on the first clock state in order to pass the clock signal. The second and fourth subcircuits pull the first and second nodes, respectively, to complementary voltages based on the second clock state to pass the clock signal. The first node passes the clock signal or gates the clock signal based on the enable signal.

    Abstract translation: 时钟门控器包括接收使能信号并且包括第一和第二子电路的第一逻辑电路。 时钟门控器还包括与第一逻辑电路共享第一和第二节点并且包括第三和第四子电路的锁存器。 第一逻辑电路和锁存器接收在第一和第二时钟状态之间变化的时钟信号。 第一和第三子电路分别将第一和第二节点分别拉到基于第一时钟状态的公共预充电电压以便传递时钟信号。 第二和第四子电路分别将第一和第二节点分别拉到基于第二时钟状态的互补电压以传递时钟信号。 第一节点通过时钟信号或基于使能信号对时钟信号进行门控。

    System and method for printing images on labels and forms in a printing device
    6.
    发明授权
    System and method for printing images on labels and forms in a printing device 失效
    用于在打印设备中的标签和表格上打印图像的系统和方法

    公开(公告)号：US06977749B2

    公开(公告)日：2005-12-20

    申请号：US09798531

    申请日：2001-03-02

    Applicant: Kevin G. Currans ,  Jason T. Su

    Inventor： Kevin G. Currans ,  Jason T. Su

    IPC: G06K15/02 ,  G06F15/00 ,  B42D15/00 ,  G06K7/00

    CPC classification number: G06K15/02 ,  G06K15/024 ,  G06K2215/0097

    Abstract: An apparatus and method are disclosed herein for printing images on labels attached to a backing in a printing device. An apparatus and method for printing an image in a predetermined area of a form are also disclosed. Further characteristics and features of the present invention are additionally disclosed herein, as are exemplary alternative embodiments. This abstract is not to be used in the interpretation of any of the claims.

    Abstract translation: 本文公开了一种用于在连接到印刷装置中的背衬的标签上打印图像的装置和方法。 还公开了一种在形式的预定区域中打印图像的装置和方法。 本文另外公开了本发明的其它特征和特征，以及示例性替代实施例。 本摘要不用于任何权利要求的解释。

    Stationary Massage Device, System and Methods for Soft Tissue Strain Release
    8.
    发明申请
    Stationary Massage Device, System and Methods for Soft Tissue Strain Release 审中-公开

    公开(公告)号：US20190029908A1

    公开(公告)日：2019-01-31

    申请号：US15658413

    申请日：2017-07-25

    Applicant: Jason T. Su

    Inventor： Jason T. Su

    IPC: A61H1/02 ,  A61H7/00 ,  A61F7/00 ,  A61F7/03

    Abstract: Disclosed are stationary massage device, system and methods for self-administrated or assisted soft tissue strain release (including trigger point therapy, strain-and-counterstrain therapy and neuromuscular release). The massage device comprises a body, wherein the body may include branches, each having flat surfaces, edges, ridges or corners. The surfaces, edges and ridges may be pushed along the myofilament direction of the soft tissues to produce pressing, rubbing, stretching and pulling actions on the soft tissues as stripping massages. The system can be configured to form different geometric shapes, and made of different materials of different firmness. The system can be further configured to perform unheated, or heated massages; and cooling treatments. In addition to being used alone, the system can be mounted on a piece of wall, a standing frame, furniture or a garment.

    PROGRAMMABLE RESISTANCE-MODULATED WRITE ASSIST FOR A MEMORY DEVICE
    9.
    发明申请
    PROGRAMMABLE RESISTANCE-MODULATED WRITE ASSIST FOR A MEMORY DEVICE 有权
    用于存储器件的可编程电阻调制写入器

    公开(公告)号：US20140177356A1

    公开(公告)日：2014-06-26

    申请号：US13726800

    申请日：2012-12-26

    Applicant: Jason T. Su ,  Bin Liang

    Inventor： Jason T. Su ,  Bin Liang

    IPC: G11C7/10

    CPC classification number: G11C7/1096 ,  G11C11/419

    Abstract: Providing for improved write processes of a semiconductor memory are disclosed herein. By way of example, a programmable write assist can be provided that includes partially discharging a supply voltage applied to a memory cell. Partially discharging the supply voltage can improve write speeds to the memory cell, as well as improve reliability of the write process. A write assist circuit can cause the discharging in response to a resistance-modulated signal. Moreover, the resistance-modulated signal can be configured to control an amount or speed of the discharging of the supply voltage. Further, modulation control can be provided to mitigate discharging of the supply voltage beyond a target level, to reduce data loss in a target data cell or an adjacent data cell.

    Abstract translation: 本文公开了提供半导体存储器的改进的写入处理。 作为示例，可以提供可编程写入辅助，其包括部分地放电施加到存储器单元的电源电压。 部分放电电源可以提高对存储单元的写入速度，并提高写入过程的可靠性。 写辅助电路可以响应于电阻调制信号而引起放电。 此外，电阻调制信号可以被配置为控制电源电压的放电的量或速度。 此外，可以提供调制控制以减轻电源电压超出目标电平的放电，以减少目标数据单元或相邻数据单元中的数据丢失。

    Method and apparatus for timing closure
    10.
    发明授权
    Method and apparatus for timing closure 失效
    用于定时关闭的方法和装置

    公开(公告)号：US08689162B2

    公开(公告)日：2014-04-01

    申请号：US13235908

    申请日：2011-09-19

    Applicant: Jason T. Su ,  Winston Lee

    Inventor： Jason T. Su ,  Winston Lee

    IPC: G06F17/50

    CPC classification number: G06F17/5045 ,  G06F17/5031 ,  G06F2217/84 ,  H03K5/159 ,  H03K2005/00013

    Abstract: Aspects of the disclosure provide a circuit, such as an integrated circuit. The circuit includes a first circuit and a second circuit. The second circuit includes a delay circuit configured to cause the second circuit to have substantially matched delay characteristics of the first circuit in response to at least one parameter change of manufacturing, environmental and operational parameters, such as process variation, temperature variation, and supply voltage variation.

    Abstract translation: 本公开的方面提供了诸如集成电路的电路。 电路包括第一电路和第二电路。 第二电路包括延迟电路，其被配置为响应于制造，环境和操作参数（例如过程变化，温度变化和电源电压）的至少一个参数变化，使得第二电路具有基本匹配的第一电路的延迟特性 变异。

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