公开(公告)号：US08242576B2

公开(公告)日：2012-08-14

申请号：US11186581

申请日：2005-07-21

Applicant: Jian-Hong Lin ,  Kang-Cheng Lin ,  Tzu-Li Lee

Inventor： Jian-Hong Lin ,  Kang-Cheng Lin ,  Tzu-Li Lee

IPC: H01L23/52

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure prevents energy that is used to blow a fuse from causing damage. The semiconductor structure includes a device, guard ring, and at least one protection layer. The device is constructed on the semiconductor substrate underneath the fuse. The seal ring, which surrounds the fuse, is constructed on at least one metal layer between the device and the fuse for confining the energy therein. The protection layer is formed within the seal ring, on at least one metal layer between the device and the fuse for shielding the device from being directly exposed to the energy.

Abstract translation: 半导体结构防止用于熔断保险丝的能量造成损坏。 半导体结构包括器件，保护环和至少一个保护层。 该器件构造在保险丝下方的半导体衬底上。 围绕熔丝的密封环构造在设备和保险丝之间的至少一个金属层上，以将能量限制在其中。 保护层形成在密封环内，在设备和保险丝之间的至少一个金属层上，用于屏蔽器件不会直接暴露于能量。

公开(公告)号：US07667289B2

公开(公告)日：2010-02-23

申请号：US11091508

申请日：2005-03-29

Applicant: Jian-Hong Lin ,  Kang-Cheng Lin

Inventor： Jian-Hong Lin ,  Kang-Cheng Lin

IPC: H01L21/326

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A laser fuse structure for a semiconductor device, the laser fuse structure having an array of laser fuses wherein one or more of the fuses in the array have a tortuous fuse line extending between first and second connectors that connect the fuse to an underlying circuit area.

Abstract translation: 一种用于半导体器件的激光熔丝结构，所述激光熔丝结构具有激光熔丝阵列，其中阵列中的一个或多个熔丝具有在将熔丝连接到下面的电路区域的第一和第二连接器之间延伸的曲折熔丝。

公开(公告)号：US20070018279A1

公开(公告)日：2007-01-25

申请号：US11186581

申请日：2005-07-21

Applicant: Jian-Hong Lin ,  Kang-Cheng Lin ,  Tzu-Li Lee

Inventor： Jian-Hong Lin ,  Kang-Cheng Lin ,  Tzu-Li Lee

IPC: H01L29/00

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure prevents energy that is used to blow a fuse from causing damage. The semiconductor structure includes a device, guard ring, and at least one protection layer. The device is constructed on the semiconductor substrate underneath the fuse. The seal ring, which surrounds the fuse, is constructed on at least one metal layer between the device and the fuse for confining the energy therein. The protection layer is formed within the seal ring, on at least one metal layer between the device and the fuse for shielding the device from being directly exposed to the energy.

Abstract translation: 半导体结构防止用于熔断保险丝的能量造成损坏。 半导体结构包括器件，保护环和至少一个保护层。 该器件构造在保险丝下方的半导体衬底上。 围绕熔丝的密封环构造在设备和保险丝之间的至少一个金属层上，以将能量限制在其中。 保护层形成在密封环内，在设备和保险丝之间的至少一个金属层上，用于屏蔽器件不会直接暴露于能量。

公开(公告)号：US20060226507A1

公开(公告)日：2006-10-12

申请号：US11091508

申请日：2005-03-29

Applicant: Jian-Hong Lin ,  Kang-Cheng Lin

Inventor： Jian-Hong Lin ,  Kang-Cheng Lin

IPC: H01L29/00

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A laser fuse structure for a semiconductor device, the laser fuse structure having an array of laser fuses wherein one or more of the fuses in the array have a tortuous fuse line extending between first and second connectors that connect the fuse to an underlying circuit area.

Abstract translation: 一种用于半导体器件的激光熔丝结构，所述激光熔丝结构具有激光熔丝阵列，其中阵列中的一个或多个熔丝具有在将熔丝连接到下面的电路区域的第一和第二连接器之间延伸的曲折熔丝。

公开(公告)号：US08541264B2

公开(公告)日：2013-09-24

申请号：US13548039

申请日：2012-07-12

Applicant: Jian-Hong Lin ,  Kang-Cheng Lin ,  Tzu-Li Lee

Inventor： Jian-Hong Lin ,  Kang-Cheng Lin ,  Tzu-Li Lee

IPC: H01L21/82

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a semiconductor structure is provided to prevent energy that is used to blow at least one fuse formed on a metal layer above a semiconductor substrate from causing damage on the structure. The semiconductor structure includes a device, guard ring, protection ring, and at least one protection layer. The device is constructed on the semiconductor substrate underneath the fuse. A seal ring, which surrounds the fuse, is constructed on at least one metal layer between the device and the fuse for confining the energy therein. The protection layer is formed within the seal ring, on at least one metal layer between the device and the fuse for shielding the device from being directly exposed to the energy.

Abstract translation: 提供一种用于形成半导体结构的方法，以防止用于吹送形成在半导体衬底上的金属层上的至少一个熔丝的能量引起对结构的损坏。 半导体结构包括器件，保护环，保护环和至少一个保护层。 该器件构造在保险丝下方的半导体衬底上。 围绕熔丝的密封环构造在设备和保险丝之间的至少一个金属层上，以将能量限制在其中。 保护层形成在密封环内，在设备和保险丝之间的至少一个金属层上，用于屏蔽器件不会直接暴露于能量。

公开(公告)号：US20120276732A1

公开(公告)日：2012-11-01

申请号：US13548039

申请日：2012-07-12

Applicant: Jian-Hong Lin ,  Kang-Cheng Lin ,  Tzu-Li Lee

Inventor： Jian-Hong Lin ,  Kang-Cheng Lin ,  Tzu-Li Lee

IPC: H01L21/768

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a semiconductor structure is provided to prevent energy that is used to blow at least one fuse formed on a metal layer above a semiconductor substrate from causing damage on the structure. The semiconductor structure includes a device, guard ring, protection ring, and at least one protection layer. The device is constructed on the semiconductor substrate underneath the fuse. A seal ring, which surrounds the fuse, is constructed on at least one metal layer between the device and the fuse for confining the energy therein. The protection layer is formed within the seal ring, on at least one metal layer between the device and the fuse for shielding the device from being directly exposed to the energy.

Abstract translation: 提供一种用于形成半导体结构的方法，以防止用于吹送形成在半导体衬底上的金属层上的至少一个熔丝的能量引起对结构的损坏。 半导体结构包括器件，保护环，保护环和至少一个保护层。 该器件构造在保险丝下方的半导体衬底上。 围绕熔丝的密封环构造在设备和保险丝之间的至少一个金属层上，以将能量限制在其中。 保护层形成在密封环内，在设备和保险丝之间的至少一个金属层上，用于屏蔽器件不会直接暴露于能量。

公开(公告)号：US08755000B2

公开(公告)日：2014-06-17

申请号：US13471425

申请日：2012-05-14

Applicant: Jian-Hong Lin

Inventor： Jian-Hong Lin

IPC: G02F1/13 ,  G02F1/1333 ,  G02F1/1343

CPC classification number: G02F1/1345 ,  G02F1/136259 ,  G02F2001/136272

Abstract: A display panel including a first substrate, a second substrate, and a liquid crystal layer. The first substrate comprises a display region and a peripheral circuit region adjacent to the display region, and the first substrate includes a pixel array, a plurality of test shorting bars, and a plurality of wires. The pixel array is disposed in the display region. The test shorting bars are disposed in the peripheral circuit region. The wires are disposed in the peripheral circuit region and electrically connected with the pixel array. Moreover, at least one wire and one of the test shorting bars respectively share a part for connecting with each other and forming a common trace. Additionally, the second substrate is disposed opposite to the first substrate. The liquid crystal layer is disposed between the first substrate and the second substrate.

Abstract translation: 一种显示面板，包括第一基板，第二基板和液晶层。 第一衬底包括与显示区域相邻的显示区域和外围电路区域，并且第一衬底包括像素阵列，多个测试短路条和多条电线。 像素阵列设置在显示区域中。 测试短路棒设置在外围电路区域中。 电线布置在外围电路区域中并与像素阵列电连接。 此外，至少一根线和一个测试短路棒分别共享用于彼此连接并形成公共痕迹的部分。 另外，第二基板与第一基板相对设置。 液晶层设置在第一基板和第二基板之间。

公开(公告)号：US20120205206A1

公开(公告)日：2012-08-16

申请号：US13342922

申请日：2012-01-03

Applicant: Jian-Yu Chen ,  Ming-Liang Wong ,  Chih-Ming Yu ,  Wun-Ya Gao ,  Jian-Hong Lin

Inventor： Jian-Yu Chen ,  Ming-Liang Wong ,  Chih-Ming Yu ,  Wun-Ya Gao ,  Jian-Hong Lin

IPC: F16F9/08

CPC classification number: F16F9/096

Abstract: A hydraulic buffer device includes a first chamber, a second chamber, and a buffering space disposed under the first and second chambers, an air bladder disposed in the buffering space, an oil chamber disposed above the first and second chambers and divided by a piston into upper and lower chamber portions, and an annular passage disposed around the oil chamber. When the piston is moved downwardly within the oil chamber, the hydraulic oil flows from the lower chamber portion into the buffering space via the first chamber to contract the air bladder so that, upon expansion of the air bladder, air pressure in the air bladder pushes the hydraulic oil to flow from the buffering space into the upper chamber portion via the second chamber and the annular passage.

Abstract translation: 液压缓冲装置包括第一室，第二室和设置在第一和第二室下方的缓冲空间，设置在缓冲空间中的空气囊，设置在第一和第二室上方并由活塞分隔的油室 上室和下室部分以及设置在油室周围的环形通道。 当活塞在油室内向下移动时，液压油经由第一腔室从下室部分流入缓冲空间，以使气囊收缩，使得当气囊膨胀时，空气囊中的空气压力推动 所述液压油经由所述第二室和所述环形通道从所述缓冲空间流入所述上室部。

公开(公告)号：US20110069806A1

公开(公告)日：2011-03-24

申请号：US12565226

申请日：2009-09-23

Applicant: Yi-Suei Liao ,  Jian-Hong Lin

Inventor： Yi-Suei Liao ,  Jian-Hong Lin

IPC: G11C19/00 ,  H03L5/00

CPC classification number: G11C19/28 ,  G09G2300/0408 ,  G09G2300/0417 ,  G09G2310/0286 ,  G09G2320/043 ,  G11C19/184

Abstract: The present invention relates to a pull-down control circuit and a shift register of using same. In one embodiment, the pull-down control circuit includes a release circuit and four transistors T4, T5, T6 and T7 electrically coupled to each other. The release circuit is adapted for causing the transistor T5 to be turned on and off alternately, thereby substantially reducing the stress thereon, improving the reliability and prolonging the lifetime of the shift register.

Abstract translation: 本发明涉及一种下拉控制电路和使用它的移位寄存器。 在一个实施例中，下拉控制电路包括释放电路和彼此电耦合的四个晶体管T4，T5，T6和T7。 释放电路适于使晶体管T5交替地导通和截止，从而大大降低其上的应力，提高可靠性并延长移位寄存器的寿命。

公开(公告)号：US20100327456A1

公开(公告)日：2010-12-30

申请号：US12879770

申请日：2010-09-10

Applicant: Hsien-Wei Chen ,  Jian-Hong Lin ,  Tzu-Li Lee

Inventor： Hsien-Wei Chen ,  Jian-Hong Lin ,  Tzu-Li Lee

IPC: H01L23/52

CPC classification number: H01L21/7682 ,  H01L21/76828 ,  H01L21/76829 ,  H01L2221/1047

Abstract: An interconnect structure of an integrated circuit having improved reliability and a method for forming the same are provided. The method includes providing a substrate, forming a dielectric layer overlying the substrate, performing a first shrinking process, wherein the dielectric layer shrinks and has a first shrinkage rate, forming a conductive feature in the dielectric layer after the step of performing the first shrinking process, and performing a second shrinking process after the step of forming the conductive feature, wherein the dielectric layer substantially shrinks and has a second shrinkage rate.

Abstract translation: 提供了具有改善的可靠性的集成电路的互连结构及其形成方法。 该方法包括提供衬底，形成覆盖在衬底上的电介质层，执行第一收缩过程，其中电介质层收缩并具有第一收缩率，在执行第一收缩过程的步骤之后在介电层中形成导电特征 并且在形成导电特征的步骤之后执行第二收缩过程，其中介电层基本上收缩并且具有第二收缩率。