公开(公告)号：US10884481B2

公开(公告)日：2021-01-05

申请号：US15942170

申请日：2018-03-30

Applicant: KONICA MINOLTA LABORATORY U.S.A., INC.

Inventor： Thien Nguyen ,  Shaun Pinney ,  Hiroyasu Ito

IPC: G06F1/32 ,  G06F1/3287 ,  G06F12/0875 ,  G06F12/0866

Abstract: An apparatus and method are disclosed for improving power savings by accelerating suspend and resume operations. The apparatus having a main integrated circuit, the integrated circuit having a context area, a context snooper, and a context cache, the context area configured to store context change information, the context snooper configured to monitor the context change information, and the context cache configured to store at least a portion of the context change information being monitored by the context snooper; and a memory, the memory configured to receive the at least a portion of the context change information from the context cache upon a suspend process signal to the main integrated circuit, to retain contents during the main integrated circuit suspend, and restore the at least a portion of the context change information to the context cache and/or the context area upon a resume process signal to the main integrated circuit.

公开(公告)号：US10459508B2

公开(公告)日：2019-10-29

申请号：US15610503

申请日：2017-05-31

Applicant: KONICA MINOLTA LABORATORY U.S.A., INC.

Inventor： Thien Nguyen ,  Sarma Sista

IPC: G06F1/32 ,  G06F1/324 ,  G06F13/42 ,  G06F1/3287 ,  G06F1/3234 ,  G06F13/38 ,  G06F1/3296 ,  G06F1/3203

Abstract: A low frequency power management bus, a method of power management of a device, and a non-transitory computer readable program code configured to execute a power management process for a device are disclosed. The power management bus including a bus, and a plurality of power nodes connected to the bus, each of the plurality of power nodes including power management control logic, a power regulator, and a power policy, and wherein the plurality of power nodes are arranged in a topology with at least one node of the plurality of nodes being designated as a super power node, the super power node configured to be connected either directly or through another power node to each of the plurality of power nodes within the topology.