Yield enhancement techniques for photonic communications platform

    公开(公告)号:US12130484B2

    公开(公告)日:2024-10-29

    申请号:US17942404

    申请日:2022-09-12

    CPC classification number: G02B6/4274 G02B6/4249 G02B6/4286

    Abstract: Described herein are techniques for yield enhancement in photonic communications platforms. A photonic communication platform may include a photonic substrate patterned with a plurality of photonic modules including at least first and second photonic modules, wherein the first and second photonic modules are copies of a common template photonic module. Yield enhancement may be accomplished using photonic redundancy and/or electronic redundancy. Photonic redundancy may involve redundant optical lanes provided in parallel to primary optical lanes. Electronic redundancy may involve use of additional electronic circuits or wires running in parallel to electronic circuits or wires. Defective circuits may be disabled to prevent negative impacts on other parts of the electronic system. This can be done by providing power-isolating switches that completely disable and isolate the defective circuits.

    OPTICAL COMMUNICATION SUBSTRATE USING GLASS INTERPOSER

    公开(公告)号:US20240353614A1

    公开(公告)日:2024-10-24

    申请号:US18638820

    申请日:2024-04-18

    CPC classification number: G02B6/12002 H04B10/40 H04B10/802 G02B2006/12038

    Abstract: Described herein photonic interconnects based on glass interposers. Glass interposers of the types described herein are used to photonically interconnect multiple smaller photonic integrated circuits (PIC), as opposed to using a single, larger PIC. The typical yield of a glass interposer is significantly higher than the yield of a PIC. This is because glass interposers are passive in nature, while PICs include active photonic elements. Active photonic components (e.g., photonic transceivers and switches) tend to be more susceptible to manufacturing defects than passive photonic components (e.g., waveguides and couplers) because active components require additional manufacturing steps (e.g., ion implantation, sputtering, epitaxial growth, etc.). The approach described herein improves performance because instead of having to slice a large number of continuous reticles from a wafer, one can pick and choose reticles known to have yielded.

    Computer chassis
    6.
    外观设计

    公开(公告)号:USD1018522S1

    公开(公告)日:2024-03-19

    申请号:US29801802

    申请日:2021-07-30

    Abstract: FIG. 1 is a top, front, left side perspective view of a computer chassis;
    FIG. 2 is a front view thereof;
    FIG. 3 is a rear view thereof;
    FIG. 4 is a left side view thereof;
    FIG. 5 is a right side view thereof;
    FIG. 6 is a top view thereof;
    FIG. 7 is a bottom view thereof;
    FIG. 8 shows the front view of FIG. 2 on an enlarged scale;
    FIG. 9 shows the rear view of FIG. 3 on an enlarged scale;
    FIG. 10 shows a dash-dot-dot rectangle identifying a portion of FIG. 8; and,
    FIG. 11 shows the portion identified in FIG. 10 on a further enlarged scale.
    The dot-dash broken lines in the figures represent boundaries of the claimed design and form no part thereof. The “11” and the associated dash-dot-dot line shown in FIG. 10, as well as the dash-dot-dot rectangle identifying and displaying the enlarged region, form no part of the claimed design. All other broken lines and surfaces without surface shading illustrate portions of the computer chassis that form no part of the claimed design.

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