公开(公告)号：US12222890B2

公开(公告)日：2025-02-11

申请号：US17846305

申请日：2022-06-22

Applicant: Liqid Inc.

Inventor： James Scott Cannata ,  Christopher R. Long ,  Phillip Clark ,  Sumit Puri

IPC: G06F13/42 ,  G06F9/4401

Abstract: A method of programming a fabric-coupled FPGA device includes instructing a communication fabric to establish a first logical partition segregating a first set of communication switch ports within the communication fabric that includes the management processor and a target device comprising a memory device configured to program a field-programmable gate array (FPGA). The method includes directing configuration data configured to program the FPGA to the target device over the first logical partition. The method includes instructing the communication fabric to remove the first logical partition in the communication fabric, wherein the configuration data remains stored at the target device after removal of the first logical partition. The method includes instructing the communication fabric to establish a second logical partition segregating a second set of communication switch ports within the communication fabric that includes a selected device and the target device that stores the configuration data.

公开(公告)号：US12204476B2

公开(公告)日：2025-01-21

申请号：US18151797

申请日：2023-01-09

Applicant: Liqid Inc.

Inventor： James Scott Cannata ,  Christopher R. Long ,  Sumit Puri ,  Bryan Schramm

IPC: G06F13/28 ,  G06F13/40 ,  G06F13/42

Abstract: Computing architectures, platforms, and systems are provided herein. In one example, system is provided. The system includes a management processor configured to initiate a communication arrangement between a first endpoint device coupled to a communication fabric and a second endpoint device coupled to the communication fabric. The communication arrangement is configured to redirect a transfer from the first endpoint device based on an address corresponding to an address range of the second endpoint device without passing the transfer through a host processor coupled to the communication fabric that executes an application initiating the transfer.

公开(公告)号：US20240184634A1

公开(公告)日：2024-06-06

申请号：US18436283

申请日：2024-02-08

Applicant: Liqid Inc.

Inventor： Christopher R. Long ,  James Scott Cannata ,  Jason Breakstone

IPC: G06F9/50 ,  G06F3/0482 ,  G06F3/0484 ,  G06F9/451 ,  G06F9/54 ,  G06F12/02

CPC classification number: G06F9/5044 ,  G06F3/0482 ,  G06F3/0484 ,  G06F9/5016 ,  G06F9/5061 ,  G06F9/5077 ,  G06F9/54 ,  G06F12/02 ,  G06F9/451 ,  G06F2203/04803 ,  G06F2213/0026

Abstract: Communication fabric-coupled computing architectures, platforms, and systems are provided herein. In one example, an apparatus includes a management entity configured to establish a compute unit comprising components from among a plurality of physical computing components by at least instructing a communication fabric communicatively coupling the plurality of physical computing components to establish logical isolation within the communication fabric to form the compute unit. Responsive to an indication of a change in workload associated with at least a software component deployed to a processing element of the compute unit, the management entity is configured to adjust the logical isolation to alter a quantity of the plurality of physical computing components in the compute unit in accordance with the change in the workload.

公开(公告)号：US11609873B2

公开(公告)日：2023-03-21

申请号：US17461149

申请日：2021-08-30

Applicant: Liqid Inc.

Inventor： James Scott Cannata ,  Christopher R. Long ,  Sumit Puri ,  Bryan Schramm

IPC: G06F13/28 ,  G06F13/42 ,  G06F13/40

Abstract: Computing architectures, platforms, and systems are provided herein. In one example, system is provided. The system includes a first processor configured to initiate a communication arrangement between a first peripheral component interconnect express (PCIe) device and a second PCIe device. The communication arrangement is configured to detect transfers from the first PCIe device to one or more addresses corresponding to an address range of the second PCIe device, and redirect the transfers to the second PCIe device without passing the transfers through a second processor that initiates the transfers.

公开(公告)号：US11119957B2

公开(公告)日：2021-09-14

申请号：US16810944

申请日：2020-03-06

Applicant: Liqid Inc.

Inventor： James Scott Cannata ,  Christopher R. Long ,  Sumit Puri ,  Bryan Schramm

IPC: G06F13/28 ,  G06F13/42

Abstract: Computing architectures, platforms, and systems are provided herein. In one example, system is provided. The system includes a first processor configured to initiate a communication arrangement between a first peripheral component interconnect express (PCIe) device and a second PCIe device. The communication arrangement is configured to detect transfers from the first PCIe device to one or more addresses corresponding to an address range of the second PCIe device, and redirect the transfers to the second PCIe device without passing the transfers through a second processor that initiates the transfers.

公开(公告)号：US20210191894A1

公开(公告)日：2021-06-24

申请号：US17162922

申请日：2021-01-29

Applicant: Liqid Inc.

Inventor： James Scott Cannata ,  German Kazakov ,  Christopher R. Long ,  Jason Breakstone

IPC: G06F13/40 ,  G06T1/20 ,  G06F13/42 ,  G06F12/02 ,  G06F9/50 ,  G06F13/28

Abstract: Disaggregated computing architectures, platforms, and systems are provided herein. In one example, a method includes receiving user input to establish a compute unit comprising a host processor and at least two graphics processing units (GPUs) having a peer-to-peer capability. The method also includes instructing a management element for a communication fabric to form the compute unit and communicatively couple the host processor and the at least two GPUs over the communication fabric. The method also includes instructing the management element to establish an isolation function to form the peer arrangement between the at least two GPUs in the communication fabric, where the isolation function isolates a first address domain associated with the at least two GPUs from at least a second address domain associated with the host processor by at least establishing synthetic devices representing the at least two GPUs in the second address domain.

公开(公告)号：US10936521B2

公开(公告)日：2021-03-02

申请号：US16893638

申请日：2020-06-05

Applicant: Liqid Inc.

Inventor： Christopher R. Long

IPC: G06F3/00 ,  G06F13/40 ,  H04L12/743

Abstract: Computing architectures, platforms, and systems are provided herein. In one example, a system is provided. The system includes a communication arrangement for peripheral component interconnect express (PCIe) traffic transferred over a communication fabric. The communication arrangement establishes an expanded address that provides a quantity of port identifiers to a host greater than indicated by a quantity of bits in a port field of the PCIe traffic, where the expanded address employs one or more bits of the PCIe traffic other than the port field. The communication arrangement detects a transfer among the PCIe traffic issued by the host having the expanded address corresponding to a destination. Based on the expanded address, the communication arrangement identifies routing information to route the transfer over the communication fabric to the destination.

公开(公告)号：US10795842B2

公开(公告)日：2020-10-06

申请号：US15848248

申请日：2017-12-20

Applicant: Liqid Inc.

Inventor： Jason Breakstone ,  Christopher R. Long ,  German Kazakov ,  James Scott Cannata

IPC: G06F13/40 ,  G06T1/20 ,  G06F13/42 ,  G06F12/02 ,  G06F9/50 ,  G06F13/28

Abstract: Disaggregated computing architectures, platforms, and systems are provided herein. In one example, a data system is provided. The data system includes a first assembly comprising a plurality of modular storage bays populated with one or more graphics processing modules each including a graphics processing unit (GPU), wherein the plurality of modular storage bays each comprise a bay connector that includes a bay Peripheral Component Interconnect Express (PCIe) connection. The first assembly further comprises PCIe switch circuitry configured to communicatively couple the bay PCIe connections to a PCIe fabric over one or more external PCIe links.

公开(公告)号：US20200296853A1

公开(公告)日：2020-09-17

申请号：US16876749

申请日：2020-05-18

Applicant: Liqid Inc.

Inventor： Bryan Schramm ,  Andrew Rudolph Heyd ,  Brenden Michael Rust ,  Christopher R. Long ,  Sumit Puri

IPC: H05K7/14 ,  G06F1/18

Abstract: A storage card insertable into a host system is provided that includes a plurality of storage devices connectors. The storage card include slot offset features to offset a circuit board of the storage card from a host system slot alignment. This offset provides for storage device connector placement on both sides of the storage card. The storage card also can include a Peripheral Component Interconnect Express (PCIe) switch circuit configured to communicatively couple the PCIe signaling of the plurality of storage device connectors and PCIe signaling of a host connector of the storage card, where the PCIe switch circuit is configured to receive storage operations over the PCIe signaling of the host connector of the storage card and transfer the storage operations for delivery over the PCIe signaling of selected ones of the plurality of storage device connectors.

公开(公告)号：US10585827B1

公开(公告)日：2020-03-10

申请号：US16267623

申请日：2019-02-05

Applicant: Liqid Inc.

Inventor： James Scott Cannata ,  Christopher R. Long ,  Sumit Puri ,  Bryan Schramm

IPC: G06F13/28 ,  G06F13/42

Abstract: Computing architectures, platforms, and systems are provided herein. In one example, a computing system is provided. The computing system includes a management processor configured to initiate a peer-to-peer arrangement between a first peripheral component interconnect express (PCIe) device and a second PCIe device over a PCIe fabric comprising one or more PCIe switches. The peer-to-peer arrangement is established to detect data transfers from the first PCIe device directed to addresses corresponding to an address range established for the second PCIe device by a peer-to-peer management entity executed on a host processor, and redirect the data transfers over the PCIe fabric to the second PCIe device such that the data transfers are received by the second PCIe device without passing through the host processor.