公开(公告)号：US11948895B2

公开(公告)日：2024-04-02

申请号：US17810625

申请日：2022-07-04

Applicant: MEDIATEK INC.

Inventor： Tzu-Hung Lin ,  Chia-Cheng Chang ,  I-Hsuan Peng ,  Nai-Wei Liu

IPC: H01L23/00 ,  H01L23/043 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/562 ,  H01L23/043 ,  H01L23/13 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5383 ,  H01L24/16 ,  H01L25/0655 ,  H01L23/5385 ,  H01L2224/16227

Abstract: A semiconductor package structure includes a substrate having a wiring structure. A first semiconductor die is disposed over the substrate and is electrically coupled to the wiring structure. A second semiconductor die is disposed over the substrate and is electrically coupled to the wiring structure, wherein the first semiconductor die and the second semiconductor die are arranged side-by-side. Holes are formed on a surface of the substrate, wherein the holes are located within a projection of the first semiconductor die or the second semiconductor die on the substrate. Further, a molding material surrounds the first semiconductor die and the second semiconductor die, and surfaces of the first semiconductor die and the second semiconductor die facing away from the substrate are exposed by the molding material.

公开(公告)号：US11670596B2

公开(公告)日：2023-06-06

申请号：US17208175

申请日：2021-03-22

Applicant: MEDIATEK INC.

Inventor： Yi-Lin Tsai ,  Wen-Sung Hsu ,  I-Hsuan Peng ,  Yi-Jou Lin

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/5381 ,  H01L23/49816 ,  H01L24/20 ,  H01L24/73 ,  H01L2224/224 ,  H01L2224/73104

Abstract: A semiconductor package structure includes a substrate, a first redistribution layer, a second redistribution layer, a bridge structure, a first semiconductor component, and a second semiconductor component. The first redistribution layer is over the substrate. The second redistribution layer is over the first redistribution layer. The bridge structure is between the first redistribution layer and the second redistribution layer, wherein the bridge structure includes an active device. The first semiconductor component and the second semiconductor component are located over the second redistribution layer, wherein the first semiconductor component is electrically coupled to the second semiconductor component through the second redistribution layer and the bridge structure.

公开(公告)号：US20230044797A1

公开(公告)日：2023-02-09

申请号：US17973318

申请日：2022-10-25

Applicant: MediaTek Inc.

Inventor： Yao-Chun Su ,  Chih-Ching Chen ,  I-Hsuan Peng ,  Yi-Jou Lin

IPC: H01L25/16 ,  H01L23/16 ,  H01L23/31 ,  H01L23/367 ,  H01L23/538 ,  H01L23/00 ,  H01L49/02

Abstract: A semiconductor package including at least one functional die; at least one dummy die free of active circuit, wherein the dummy die comprises at least one metal-insulator-metal (MIM) capacitor; and a redistribution layer (RDL) structure interconnecting the MIM capacitor to the at least one functional die.

公开(公告)号：US10410969B2

公开(公告)日：2019-09-10

申请号：US15891481

申请日：2018-02-08

Applicant: MEDIATEK INC.

Inventor： Tzu-Hung Lin ,  Chia-Cheng Chang ,  I-Hsuan Peng

IPC: H01L23/31 ,  H01L23/538 ,  H01L23/528 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L25/18 ,  H01L21/56 ,  H01L23/367 ,  H01L25/10

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package and a second semiconductor package overlying a portion of the first semiconductor package. The first semiconductor package includes a first redistribution layer (RDL) structure, a first semiconductor die and a molding compound. The first semiconductor die is disposed on a first surface of the first RDL structure and electrically coupled to the first RDL structure. The molding compound is positioned overlying the first semiconductor die and the first surface of the first RDL structure. The second semiconductor package includes a first memory die and a second memory die vertically stacked on the first memory die. The second memory die is electrically coupled to first memory die by through silicon via (TSV) interconnects formed passing through the second memory die.

公开(公告)号：US10217723B2

公开(公告)日：2019-02-26

申请号：US15644849

申请日：2017-07-10

Applicant: MEDIATEK INC.

Inventor： Tzu-Hung Lin ,  I-Hsuan Peng ,  Nai-Wei Liu ,  Wei-Che Huang

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/538 ,  H01L29/06

Abstract: A semiconductor chip package includes a first die and a second die. The first die and second die are coplanar and disposed in proximity to each other in a side-by-side fashion. A non-straight line shaped interface gap is disposed between the first die and second die. A molding compound surrounds the first die and second die. A redistribution layer (RDL) structure is disposed on the first die, the second die and on the molding compound. The first semiconductor die is electrically connected to the second semiconductor die through the RDL structure.

公开(公告)号：US09978729B2

公开(公告)日：2018-05-22

申请号：US14986207

申请日：2015-12-31

Applicant: MediaTek Inc.

Inventor： Tzu-Hung Lin ,  I-Hsuan Peng

IPC: H01L23/02 ,  H01L25/10 ,  H01L23/00 ,  H01L25/16 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L25/105 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/16 ,  H01L2224/04042 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package including a first semiconductor die. A first molding compound surrounds the first semiconductor die. A first redistribution layer (RDL) structure is disposed on a bottom surface of the first molding compound. The first semiconductor die is coupled to the first RDL structure. A second redistribution layer (RDL) structure is disposed on a top surface of the first molding compound. A passive device is coupled to the second RDL structure.

公开(公告)号：US09941260B2

公开(公告)日：2018-04-10

申请号：US15203418

申请日：2016-07-06

Applicant: MediaTek Inc.

Inventor： Tzu-Hung Lin ,  Chi-Chin Lien ,  Nai-Wei Liu ,  I-Hsuan Peng ,  Ching-Wen Hsiao ,  Wei-Che Huang

IPC: H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L25/105 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/5389 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a first semiconductor package that includes a first semiconductor die having a first surface and a second surface opposite thereto. A first package substrate is disposed on the first surface of the first semiconductor die. A first molding compound surrounds the first semiconductor die and the first package substrate. A first redistribution layer (RDL) structure is disposed on the first molding compound, in which the first package substrate is interposed and electrically coupled between the first semiconductor die and the first RDL structure.

公开(公告)号：US20240055358A1

公开(公告)日：2024-02-15

申请号：US18383466

申请日：2023-10-24

Applicant: MEDIATEK INC.

Inventor： Yao-Chun Su ,  Chih-Jung Hsu ,  Yi-Jou Lin ,  I-Hsuan Peng

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/367 ,  H01L23/00 ,  H01L23/58 ,  H01L23/66 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/5385 ,  H01L23/562 ,  H01L23/585 ,  H01L23/66 ,  H01L25/0655 ,  H01L2223/6638 ,  H01L2223/6666

Abstract: An electronic package includes a base of a rectangular shape, and a chip package including a first interface circuit die and a second interface circuit die. The first interface circuit die and second interface circuit die are mounted on a redistribution layer structure and encapsulated within a molding compound. The chip package is mounted on a top surface of the base and rotated relative to the base above a vertical axis that is orthogonal to the top surface through a rotation offset angle. A metal ring is mounted on the top surface of the base.

公开(公告)号：US11830820B2

公开(公告)日：2023-11-28

申请号：US17553760

申请日：2021-12-16

Applicant: MEDIATEK INC.

Inventor： Yao-Chun Su ,  Chih-Jung Hsu ,  Yi-Jou Lin ,  I-Hsuan Peng

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/367 ,  H01L23/00 ,  H01L23/58 ,  H01L23/66 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/5385 ,  H01L23/562 ,  H01L23/585 ,  H01L23/66 ,  H01L25/0655 ,  H01L2223/6638 ,  H01L2223/6666

Abstract: An electronic package includes a package substrate of a rectangular shape, and a chip package including a first interface circuit die and a second interface circuit die. The first interface circuit die and second interface circuit die are mounted on a redistribution layer structure and encapsulated within a molding compound. The chip package is mounted on a top surface of the package substrate and rotated relative to the package substrate above a vertical axis that is orthogonal to the top surface through a rotation offset angle. A metal ring is mounted on the top surface of the package substrate.

公开(公告)号：US11688655B2

公开(公告)日：2023-06-27

申请号：US17182525

申请日：2021-02-23

Applicant: MEDIATEK INC.

Inventor： Chia-Cheng Chang ,  Tzu-Hung Lin ,  I-Hsuan Peng ,  Nai-Wei Liu

IPC: H01L23/053 ,  H01L23/16 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L23/538 ,  H01L25/16 ,  H01L23/00 ,  H01L25/065 ,  H01L23/04 ,  H01L25/18 ,  H01L23/433 ,  H01L23/373

CPC classification number: H01L23/053 ,  H01L23/04 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/24 ,  H01L25/0655 ,  H01L25/165 ,  H01L25/18 ,  H01L23/367 ,  H01L23/3737 ,  H01L23/4334 ,  H01L2224/24137 ,  H01L2924/19105 ,  H01L2924/3511

Abstract: A semiconductor package structure including a package substrate, at least one semiconductor die, a lid structure, a first electronic component and a heat sink is provided. The package substrate has a first surface and a second surface opposite to the first surface. The semiconductor die is on the first surface of the package substrate and is surrounded by an encapsulating layer. The lid structure surrounds and is spaced apart from the encapsulating layer. The lid structure includes a first opening that is covered by the first surface of the package substrate. The first electronic component is over the first surface of the package substrate and arranged within the first opening of the lid structure. The heat sink covers the lid structure and the semiconductor die.