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    Transceiver Architecture for Multiple Antenna Systems
    3.
    发明申请
    Transceiver Architecture for Multiple Antenna Systems 有权

    公开(公告)号：US20160373938A1

    公开(公告)日：2016-12-22

    申请号：US15249562

    申请日：2016-08-29

    Applicant: MEDIATEK INC.

    Inventor： Ju-Ya Chen ,  Jing-Hong Conan Zhan

    IPC: H04W16/28 ,  H04B7/06 ,  H04B7/08 ,  H01Q3/38

    CPC classification number: H04W16/28 ,  H01Q3/38 ,  H04B7/0695 ,  H04B7/0851 ,  H04B7/086

    Abstract: A transceiver architecture with combined digital beamforming and analog/hybrid beamforming is proposed. Digital beamforming is used for beam training with reduced overhead (switching time). It is beneficial to estimate all UE's angle of arrival (AoA) at the same time. In addition, the pilot/training signals are transmitted in a narrow band to reduce complexity. Analog/hybrid beamforming is used for data transmission with high directive gain and low complexity. The value of beamforming weights (phase shifter values) in analog domain can be based on the estimation of AoA from beam training. By using digital beamforming for beam training, combined with analog/hybrid beamforming for data transmission, effective beamforming is achieved with reduced overhead, complexity, and cost.

    Phase frequency detector and charge pump for phase lock loop fast-locking
    4.
    发明授权
    Phase frequency detector and charge pump for phase lock loop fast-locking 有权
    相位频率检测器和电荷泵用于锁相环快速锁定

    公开(公告)号：US09160353B2

    公开(公告)日：2015-10-13

    申请号：US14158657

    申请日：2014-01-17

    Applicant: Mediatek Inc.

    Inventor： Yu-Li Hsueh ,  Jing-Hong Conan Zhan

    IPC: H03L7/10 ,  H03L7/089 ,  H03L7/107

    CPC classification number: H03L7/10 ,  H03L7/0891 ,  H03L7/0896 ,  H03L7/1072

    Abstract: The present invention provides for a solution to reduce locking time with satisfactory performance without the need for significant footprint area for the phase lock loop (PLL) circuits by boosting phase frequency detector (PFD) and charge pump (CP) gains through various circuitry configurations that employ one or more flip-flops, delay elements and advanced circuitry techniques.

    Abstract translation: 本发明提供了一种解决方案，通过各种电路配置通过各种电路配置升级相位频率检测器（PFD）和电荷泵（CP）增益，提供令人满意的性能，而不需要锁相环（PLL）电路的显着占地面积， 采用一个或多个触发器，延迟元件和高级电路技术。

    Charge pump, phase frequency detector and charge pump methods
    5.
    发明授权
    Charge pump, phase frequency detector and charge pump methods 有权
    电荷泵，相频检测器和电荷泵方法

    公开(公告)号：US08766684B2

    公开(公告)日：2014-07-01

    申请号：US13769810

    申请日：2013-02-18

    Applicant: Mediatek Inc.

    Inventor： Yu-Li Hsueh ,  Yi-Hsien Cho ,  Jing-Hong Conan Zhan

    IPC: H03L7/06

    CPC classification number: H03L5/00 ,  H03L7/089 ,  H03L7/0895 ,  H03L7/0896 ,  H03L7/093

    Abstract: A phase/frequency detector for controlling a charge pump includes: a core circuit arranged to output a first phase signal and a second phase signal according to a phase/frequency difference between a reference clock signal and an input clock signal; and a timing circuit coupled to the core circuit and arranged to generate a first control signal and a second control signal for controlling the charge pump according to the first phase signal and the second phase signal, wherein only one of the first control signal and the second control signal is indicative of an enabled operation when the reference clock signal and the input clock signal are substantially identical in phase.

    Abstract translation: 用于控制电荷泵的相位/频率检测器包括：核心电路，被布置成根据参考时钟信号和输入时钟信号之间的相位/频率差输出第一相位信号和第二相位信号; 以及定时电路，其耦合到所述核心电路并被布置成根据所述第一相位信号和所述第二相位信号产生用于控制所述电荷泵的第一控制信号和第二控制信号，其中，所述第一控制信号和所述第二控制信号中的仅一个 当参考时钟信号和输入时钟信号在相位上基本上相同时，控制信号指示使能操作。

    Phase-arrayed transceiver
    9.
    发明授权
    Phase-arrayed transceiver 有权
    相位收发器

    公开(公告)号：US09473195B2

    公开(公告)日：2016-10-18

    申请号：US14741473

    申请日：2015-06-17

    Applicant: MEDIATEK INC.

    Inventor： Jing-Hong Conan Zhan ,  Chuan-Kang Liang ,  Ti-Ku Yu ,  Zhiming Deng

    IPC: H04B1/38 ,  H04B1/40 ,  H01Q3/30 ,  H01Q21/00 ,  H03F3/19 ,  H03F3/21 ,  H04B1/44

    CPC classification number: H04B1/40 ,  H01Q3/30 ,  H01Q21/0025 ,  H03F3/19 ,  H03F3/21 ,  H03F2200/294 ,  H03F2200/451 ,  H04B1/44

    Abstract: A phased-array transceiver includes: a plurality of antennas; a plurality of transceiving elements respectively coupled to the plurality of antennas; a signal processing block; and a first distributed network, coupled between the signal processing block and the transceiving elements, wherein the transceiving elements, the signal processing block, and the first distributed network are configured as a single chip, and a first transceiving path between one of the plurality of transceiving elements and the signal processing block and a second transceiving path between another of the plurality of transceiving elements and the signal processing block share at least partial signal traces of the first distributed network.

    Abstract translation: 相控阵收发器包括：多个天线; 分别耦合到所述多个天线的多个收发元件; 信号处理块; 以及耦合在所述信号处理块和所述收发元件之间的第一分布式网络，其中所述收发元件，所述信号处理块和所述第一分布式网络被配置为单个芯片，以及第一收发路径， 所述信号处理块和所述多个收发元件中的另一个之间的第二收发路径与所述信号处理块共享所述第一分布式网络的至少部分信号迹线。

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