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    Semiconductor device for use in harsh media
    1.
    发明授权
    Semiconductor device for use in harsh media 有权

    公开(公告)号：US11049784B2

    公开(公告)日：2021-06-29

    申请号：US16438799

    申请日：2019-06-12

    Applicant: Melexis Technologies NV

    Inventor： Appolonius Jacobus Van Der Wiel

    IPC: H01L23/532 ,  H01L23/31 ,  H01L21/02 ,  H01L21/56 ,  H01L23/29 ,  H01L23/522 ,  H01L23/528 ,  H01L29/04 ,  H01L29/16 ,  H01L29/84 ,  H01L35/22 ,  H01L21/768

    Abstract: A semiconductor device comprising a first and second doped semiconductor layer wherein the first layer is a monosilicon layer and the second layer is a polysilicon layer, an oxide layer covering the first and second layer, and an interconnect which electrically connects the first and second layer comprises a metal alloy which has a first part in contact with the first layer and a second part in contact with the second layer, wherein a part of the metal alloy between the first and the second part crosses over a sidewall of the second layer; at least one electronic component is formed in the first and/or second layer; the semiconductor device moreover comprises a stoichiometric passivation layer which covers the first and second layer and the oxide layer.

    Semiconductor pressure sensor
    4.
    发明授权
    Semiconductor pressure sensor 有权

    公开(公告)号：US10317297B2

    公开(公告)日：2019-06-11

    申请号：US14735369

    申请日：2015-06-10

    Applicant: MELEXIS TECHNOLOGIES NV

    Inventor： Appolonius Jacobus Van Der Wiel

    IPC: H01L29/84 ,  G01L1/18 ,  G01L9/00 ,  G01L9/06 ,  G01L19/02

    Abstract: A semiconductor pressure sensor for measuring an external pressure exerted on the sensor, including: a membrane; a first resistor connected between a first bias node and a first output node; a second resistor connected between the first bias node and a second output node; a first and second current source connected to the first resp. second output node for generating a differential voltage signal indicative of the external pressure to be measured. The resistors including piezo-resistive strips arranged in particular crystallographic directions. The circuit may have a third and four resistor pair for compensating package stress. The Piezo-resistive strips may be formed as p-doped regions within an n-well, the biasing node being electrically connected to the n-well.

    Relative and absolute pressure sensor combined on chip
    5.
    发明授权
    Relative and absolute pressure sensor combined on chip 有权

    公开(公告)号：US10031003B2

    公开(公告)日：2018-07-24

    申请号：US14956770

    申请日：2015-12-02

    Applicant: Melexis Technologies NV ,  X-FAB Semiconductor Foundries AG

    Inventor： Appolonius Jacobus Van Der Wiel ,  Uwe Schwarz ,  Rudi De Winter

    IPC: H01L21/00 ,  G01F1/34 ,  G01L9/00 ,  G01L15/00 ,  B81B7/04 ,  B81C1/00 ,  G01F15/14

    Abstract: A method for manufacturing a system in a wafer for measuring an absolute and a relative pressure includes etching a shallow and a deep cavity in the wafer. A top wafer is applied and the top wafer is thinned for forming a first respectively second membrane over the shallow respectively deep cavity, and for forming in the top wafer first respectively second bondpads at the first respectively second membrane resulting in a first respectively second sensor. Back grinding the wafer results in an opened deep cavity and a still closed shallow cavity. The first bondpads of the first sensor measure an absolute pressure and the second bondpads of the second sensor measure a relative pressure. The etching in the first step defines the edges of the first membrane and of the second membrane in respectively the sensors formed from the shallow and the deep cavity.

    Semiconductor stress sensor
    6.
    发明授权
    Semiconductor stress sensor 有权

    公开(公告)号：US11515467B2

    公开(公告)日：2022-11-29

    申请号：US17111871

    申请日：2020-12-04

    Applicant: Melexis Technologies NV

    Inventor： Appolonius Jacobus Van Der Wiel ,  Maliheh Ramezani ,  Cathleen Rooman ,  Laurent Otte ,  Johan Vergauwen

    IPC: H01L41/113 ,  G01L1/18 ,  H01L41/047 ,  H01L41/053

    Abstract: A piezo-resistor sensor includes a diffusion of a first conductivity type in a well of an opposite second type, contacts with islands in the diffusion, interconnects with the contacts, and a shield covers the diffusion between the contacts and extends over side walls of the diffusion between the contacts. Each interconnect covers the diffusion at the corresponding contact and extends over edges of the diffusion, and each island is at a side covered by its interconnect. A guard ring of the second type is around the diffusion. The shield covers the well between the diffusion and the ring and the edge of the ring facing the diffusion. If a gap between the shield and the interconnect is present, the ring bridges this gap, and/or the edges of the diffusion are completely covered by the combination of the shield and the interconnects.

    Bond pad protection for harsh media applications
    7.
    发明授权
    Bond pad protection for harsh media applications 有权

    公开(公告)号：US10262897B2

    公开(公告)日：2019-04-16

    申请号：US15883487

    申请日：2018-01-30

    Applicant: Melexis Technologies NV

    Inventor： Appolonius Jacobus Van Der Wiel

    IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768 ,  H01L23/538 ,  H01L23/532 ,  G01L19/00 ,  G01L19/14 ,  H01L23/00

    Abstract: A method for making and a semiconductor device comprises a silicon die including a metal contact region and, at least one passivation layer covering the semiconductor die and patterned such as to form an opening to the metal contact region of the semiconductor die. A continuous part of a contact layer comprises a refractory metal, and overlaps and completely covers the opening in the at least one passivation layer to contact the metal contact region in the opening and adhere to the at least one passivation layer along the entire edge of the continuous part. The contact layer comprises at least an adhesion layer and at least a diffusion barrier layer. A noble metal layer is arranged over the contact layer and completely covers the continuous part to adhere to the at least one passivation layer around the edge of the continuous part.

    Method and Device for Sensing Isotropic Stress and Providing a Compensation for the Piezo-Hall Effect
    8.
    发明申请
    Method and Device for Sensing Isotropic Stress and Providing a Compensation for the Piezo-Hall Effect 有权
    用于感应各向同性应力并提供压电霍尔效应补偿的方法和装置

    公开(公告)号：US20150142342A1

    公开(公告)日：2015-05-21

    申请号：US14399623

    申请日：2013-05-07

    Applicant: MELEXIS TECHNOLOGIES NV

    Inventor： Samuel Huber ,  Johan Raman ,  Pieter Rombouts ,  Appolonius Jacobus Van Der Wiel

    IPC: G01L1/22 ,  G01L1/12

    CPC classification number: G01L1/2293 ,  G01L1/125 ,  G01L1/18 ,  G01R33/0029 ,  G01R33/0035 ,  G01R33/07

    Abstract: A method determines isotropic stress by means of a Hall element which includes a plate-shaped area made of a doped semiconductor material and comprises four contacts contacting the plate-shaped area and forming corners of a quadrangle, two neighboring corners of the quadrangle defining an edge thereof. At least one van der Pauw transresistance value in at least one van der Pauw measurement set-up of the Hall element is determined, wherein the four contacts of the Hall element form contact pairs, a contact pair comprising two contacts defining neighbouring corners of the quadrangle. One contact pair supplies a current and the other contact pair measures a voltage. A relationship between the supplied current and the measured voltage defines the Van der Pauw transresistance value. The method comprises determining a stress signal which depends on the at least one Van der Pauw transresistance value and determining isotropic stress.

    Abstract translation: 一种方法通过霍尔元件确定各向同性应力，霍尔元件包括由掺杂半导体材料制成的板状区域，并且包括接触板形区域和形成四边形角部的四个触点，四边形的两个相邻拐角限定边缘 其中。 确定霍尔元件的至少一个范德波测量装置中的至少一个范德波沃阻抗值，其中霍尔元件的四个触点形成接触对，触点对包括限定四边形的相邻角的两个触点 。 一个触点对提供电流，另一个触点对测量电压。 供电电流与测量电压之间的关系定义了范德波沃跨阻值。 该方法包括确定取决于至少一个范德高阻抗值并确定各向同性应力的应力信号。

    Method of manufacturing a sensor device and moulding support structure
    9.
    发明授权
    Method of manufacturing a sensor device and moulding support structure 有权

    公开(公告)号：US11655142B2

    公开(公告)日：2023-05-23

    申请号：US16744593

    申请日：2020-01-16

    Applicant: Melexis Technologies NV

    Inventor： Appolonius Jacobus Van Der Wiel

    IPC: B81C1/00 ,  B81C99/00 ,  B81B7/00 ,  G01L9/00

    CPC classification number: B81B7/0051 ,  B81C1/00325 ,  G01L9/0072 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81B2207/098 ,  B81C1/0046 ,  B81C2203/0154

    Abstract: A method of manufacturing a sensor device comprising: configuring a moulding support structure and a packaging mould so as to provide predetermined pathways to accommodate a moulding compound, the moulding support structure defining a first notional volume adjacent a second notional volume. An elongate sensor element and the moulding support structure are configured so that the moulding support structure fixedly carries the elongate sensor element and the elongate sensor element resides substantially in the first notional volume and extends towards the second notional volume, the elongate sensor element having an electrical contact electrically coupled to another electrical contact disposed within the second notional volume. The moulding support structure carrying (102) the elongate sensor element is disposed within the packaging mould (106). The moulding compound is then introduced (110) into the packaging mould during a predetermined period of time (112) so that the moulding compound fills the predetermined pathways, thereby filling the second notional volume and surrounding the elongate sensor element within the second notional volume without contacting the elongate sensor element.

    CMOS based devices for harsh media
    10.
    发明授权
    CMOS based devices for harsh media 有权

    公开(公告)号：US11195772B2

    公开(公告)日：2021-12-07

    申请号：US16441743

    申请日：2019-06-14

    Applicant: Melexis Technologies NV

    Inventor： Appolonius Jacobus Van Der Wiel

    IPC: H01L29/84 ,  H01L23/31 ,  H01L21/02 ,  H01L21/768 ,  H01L23/29 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/00 ,  H01L29/40 ,  H01L37/02

    Abstract: A semiconductor device comprises a first doped semiconductor layer, a second doped semiconductor layer, an oxide layer covering the first doped semiconductor layer and the second doped semiconductor layer, and an interconnect. The first doped semiconductor layer is electrically connected with the second doped semiconductor layer by means of the interconnect which crosses over a sidewall of the second doped semiconductor layer. The interconnect comprises a metal filled slit in the oxide layer. At least one electronic component is formed in the first and/or second semiconductor layer. The semiconductor device moreover comprises a passivation layer which covers the first and second doped semiconductor layers and the oxide layer.

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