-
公开(公告)号：US20250072079A1
公开(公告)日：2025-02-27
申请号：US18947497
申请日：2024-11-14
Applicant: Micron Technology, Inc.
Inventor： Thomas M. Graettinger
Abstract: The present disclosure includes methods for replacement gate formation in memory, and apparatuses and systems including memory formed accordingly. An embodiment includes forming a first oxide material in an opening through alternating layers of a second oxide material and a nitride material. An array of openings can be formed through the first oxide material formed in the opening. The layers of the nitride material can be removed. A metal material can be formed in voids resulting from the removal of the layers of the nitride material.
-
公开(公告)号：US20220415392A1
公开(公告)日：2022-12-29
申请号：US17874965
申请日：2022-07-27
Applicant: Micron Technology, Inc.
Inventor： Lorenzo Fratin , Paolo Fantini , Fabio Pellizzer , Thomas M. Graettinger
IPC: G11C13/00
Abstract: Methods, systems, and devices for decoding for a memory device are described. A decoder of a memory device may include transistors in a first layer between a memory array and a second layer that includes one or more components associated with the memory array. The second layer may include CMOS pre-decoding circuitry, among other components. The decoder may include CMOS transistors in the first layer. The CMOS transistors may control which voltage source is coupled with an access line based on a gate voltage applied to a p-type transistor and a n-type transistor. For example, a first gate voltage applied to a p-type transistor may couple a source node with the access line and bias the access line to a source voltage. A second gate voltage applied to the n-type transistor may couple a ground node with the access line and bias the access line to a ground voltage.
-
公开(公告)号：US11417394B2
公开(公告)日：2022-08-16
申请号：US17118844
申请日：2020-12-11
Applicant: Micron Technology, Inc.
Inventor： Lorenzo Fratin , Paolo Fantini , Fabio Pellizzer , Thomas M. Graettinger
Abstract: Methods, systems, and devices for decoding for a memory device are described. A decoder of a memory device may include transistors in a first layer between a memory array and a second layer that includes one or more components associated with the memory array. The second layer may include CMOS pre-decoding circuitry, among other components. The decoder may include CMOS transistors in the first layer. The CMOS transistors may control which voltage source is coupled with an access line based on a gate voltage applied to a p-type transistor and a n-type transistor. For example, a first gate voltage applied to a p-type transistor may couple a source node with the access line and bias the access line to a source voltage. A second gate voltage applied to the n-type transistor may couple a ground node with the access line and bias the access line to a ground voltage.
-
公开(公告)号：US11257838B2
公开(公告)日：2022-02-22
申请号：US16803867
申请日：2020-02-27
Applicant: Micron Technology, Inc.
Inventor： Ronald A. Weimer , Kyu S. Min , Thomas M. Graettinger , Durai Vishak Nirmal Ramaswamy
IPC: H01L27/11568 , H01L27/115
Abstract: Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area.
-
公开(公告)号：US20220189549A1
公开(公告)日：2022-06-16
申请号：US17118844
申请日：2020-12-11
Applicant: Micron Technology, Inc.
Inventor： Lorenzo Fratin , Paolo Fantini , Fabio Pellizzer , Thomas M. Graettinger
IPC: G11C13/00
Abstract: Methods, systems, and devices for decoding for a memory device are described. A decoder of a memory device may include transistors in a first layer between a memory array and a second layer that includes one or more components associated with the memory array. The second layer may include CMOS pre-decoding circuitry, among other components. The decoder may include CMOS transistors in the first layer. The CMOS transistors may control which voltage source is coupled with an access line based on a gate voltage applied to a p-type transistor and a n-type transistor. For example, a first gate voltage applied to a p-type transistor may couple a source node with the access line and bias the access line to a source voltage. A second gate voltage applied to the n-type transistor may couple a ground node with the access line and bias the access line to a ground voltage.
-
Patent Agency Ranking
公开(公告)号：US20240196765A1
公开(公告)日：2024-06-13
申请号：US18545636
申请日：2023-12-19
Applicant: Micron Technology, Inc.
Inventor： Thomas M. Graettinger , Lorenzo Fratin , Patrick M. Flynn , Enrico Varesi , Paolo Fantini
IPC: H10N70/00
CPC classification number: H10N70/8265 , H10N70/021 , H10N70/841 , H10N70/882 , H10N70/883
Abstract: Methods, systems, and devices for a memory device with laterally formed memory cells are described. A material stack that includes a conductive layer between multiple dielectric layers may be formed, where the conductive layer and dielectric layers may form a channel in a sidewall of the material stack. The channel may be filled with one or more materials, where a first side of an outermost material of the one or more materials may be exposed. An opening may be formed in the material stack that exposes a second side of at least one material of the one or more materials. The opening may be used to replace a portion of the at least one material with a chalcogenide material where the electrode materials may be formed before replacing the portion of the at least one material with the chalcogenide material.
-
公开(公告)号：US11864475B2
公开(公告)日：2024-01-02
申请号：US17332628
申请日：2021-05-27
Applicant: Micron Technology, Inc.
Inventor： Thomas M. Graettinger , Lorenzo Fratin , Patrick M. Flynn , Enrico Varesi , Paolo Fantini
IPC: H10N70/00
CPC classification number: H10N70/8265 , H10N70/021 , H10N70/841 , H10N70/882 , H10N70/883
Abstract: Methods, systems, and devices for a memory device with laterally formed memory cells are described. A material stack that includes a conductive layer between multiple dielectric layers may be formed, where the conductive layer and dielectric layers may form a channel in a sidewall of the material stack. The channel may be filled with one or more materials, where a first side of an outermost material of the one or more materials may be exposed. An opening may be formed in the material stack that exposes a second side of at least one material of the one or more materials. The opening may be used to replace a portion of the at least one material with a chalcogenide material where the electrode materials may be formed before replacing the portion of the at least one material with the chalcogenide material.
-
公开(公告)号：US20230282730A1
公开(公告)日：2023-09-07
申请号：US18196891
申请日：2023-05-12
Applicant: Micron Technology, Inc.
Inventor： Thomas M. Graettinger
CPC classification number: H01L29/66545 , H01L27/0688 , H10B63/84 , H10N70/011 , H10N70/253
Abstract: The present disclosure includes methods for replacement gate formation in memory, and apparatuses and systems including memory formed accordingly. An embodiment includes forming a first oxide material in an opening through alternating layers of a second oxide material and a nitride material. An array of openings can be formed through the first oxide material formed in the opening. The layers of the nitride material can be removed. A metal material can be formed in voids resulting from the removal of the layers of the nitride material.
-
公开(公告)号：US11652153B2
公开(公告)日：2023-05-16
申请号：US17314956
申请日：2021-05-07
Applicant: Micron Technology, Inc.
Inventor： Thomas M. Graettinger
CPC classification number: H01L29/66545 , H01L27/0688 , H01L27/2481 , H01L45/1206 , H01L45/16
Abstract: The present disclosure includes methods for replacement gate formation in memory, and apparatuses and systems including memory formed accordingly. An embodiment includes forming a first oxide material in an opening through alternating layers of a second oxide material and a nitride material. An array of openings can be formed through the first oxide material formed in the opening. The layers of the nitride material can be removed. A metal material can be formed in voids resulting from the removal of the layers of the nitride material.
-
公开(公告)号：US12159919B2
公开(公告)日：2024-12-03
申请号：US18196891
申请日：2023-05-12
Applicant: Micron Technology, Inc.
Inventor： Thomas M. Graettinger
Abstract: The present disclosure includes methods for replacement gate formation in memory, and apparatuses and systems including memory formed accordingly. An embodiment includes forming a first oxide material in an opening through alternating layers of a second oxide material and a nitride material. An array of openings can be formed through the first oxide material formed in the opening. The layers of the nitride material can be removed. A metal material can be formed in voids resulting from the removal of the layers of the nitride material.
-
-
-
-
-
-
-
-
-
Search Results
19
records
(took 0.017 seconds)
