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    REDUNDANCY AND MAJORITY VOTING IN A KEY-VALUE DATA STORAGE SYSTEM USING CONTENT ADDRESSABLE MEMORY
    2.
    发明申请
    REDUNDANCY AND MAJORITY VOTING IN A KEY-VALUE DATA STORAGE SYSTEM USING CONTENT ADDRESSABLE MEMORY 有权

    公开(公告)号：US20250046374A1

    公开(公告)日：2025-02-06

    申请号：US18915268

    申请日：2024-10-14

    Applicant: Micron Technology, Inc.

    Inventor： Tyler L. Betz ,  Manik Advani ,  Tomoko Ogura Iwasaki ,  Violante Moschiano

    IPC: G11C15/04 ,  G11C7/10

    Abstract: A memory system includes a memory device comprising a content addressable memory (CAM) block storing a plurality of stored search keys. The memory system further includes a processing device that receives an input search key and identifies, from the plurality of stored search keys in the CAM block, multiple redundant copies of a stored search key that match the input search key. The processing device further determining whether a number of the multiple redundant copies of the stored search key that match the input search key satisfies a threshold criterion. Responsive to the number of the multiple redundant copies of the stored search key that match the input search key satisfying the threshold criterion, the processing device determines a match result for the input search key.

    CONTINUOUS MEMORY PROGRAMMING OPERATIONS
    5.
    发明申请
    CONTINUOUS MEMORY PROGRAMMING OPERATIONS 有权

    公开(公告)号：US20240428872A1

    公开(公告)日：2024-12-26

    申请号：US18800552

    申请日：2024-08-12

    Applicant: Micron Technology, Inc.

    Inventor： Violante Moschiano ,  Ali Mohammadzadeh ,  Walter Di Francesco ,  Dheeraj Srinivasan

    IPC: G11C16/34 ,  G11C7/10 ,  G11C16/10 ,  G11C16/26

    Abstract: Described are systems and methods for implementing continuous memory programming operations. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of conductive lines; and a controller coupled to the memory array. The controller performs operations comprising: performing a memory programming operation with respect to a set of memory cells of the memory array, wherein the memory programming operation comprises a sequence of programming pulses applied to one or more conductive lines electrically coupled to the set of memory cells; responsive to receiving a command to perform a memory access operation, suspending the memory programming operation after performing a current programming pulse of the sequence of programming pulses, wherein the current programming pulse is performed at a first voltage level; initiating the memory access operation; and resuming the memory programming operation by performing a next programming pulse at a second voltage level that exceeds the first voltage level.

    ADJUSTABLE DELAY PROPAGATION OF A CONTROL SIGNAL TO DIFFERENT PAGE BUFFER DRIVER GROUPS
    7.
    发明申请
    ADJUSTABLE DELAY PROPAGATION OF A CONTROL SIGNAL TO DIFFERENT PAGE BUFFER DRIVER GROUPS 有权

    公开(公告)号：US20240386929A1

    公开(公告)日：2024-11-21

    申请号：US18786234

    申请日：2024-07-26

    Applicant: Micron Technology, Inc.

    Inventor： Andrea D'alessandro ,  Violante Moschiano ,  Giacomo Donati ,  Luigi Marchese

    IPC: G11C7/22 ,  G11C7/06 ,  G11C16/32

    Abstract: A microelectronic device comprises a microelectronic device structure comprising a section comprising page buffers, and an additional section horizontally neighboring the section and comprising page buffer drivers and a timing delay chain coupled to the page buffer drivers. Each of the page buffer drivers is coupled to different group of the page buffers than each other of the page buffer drivers. The timing delay chain comprises timing delay circuits coupled in series with one another. Each of the timing delay circuits is configured to adjustably delay propagation of a control signal therethrough. Memory devices, methods of operating memory devices, and electronic systems are also described.

    ON-DIE CROSS-TEMPERATURE MANAGEMENT FOR A MEMORY DEVICE
    8.
    发明申请
    ON-DIE CROSS-TEMPERATURE MANAGEMENT FOR A MEMORY DEVICE 有权

    公开(公告)号：US20240370206A1

    公开(公告)日：2024-11-07

    申请号：US18773373

    申请日：2024-07-15

    Applicant: Micron Technology, Inc.

    Inventor： Kishore Kumar Muchherla ,  Violante Moschiano ,  Akira Goda ,  Jeffrey S. McNeil ,  Jung Sheng Hoei ,  Sivagnanam Parthasarathy ,  James Fitzpatrick ,  Patrick R. Khayat

    IPC: G06F3/06

    Abstract: Control logic in a memory device receives a request to read data from a memory array of a memory device, the request comprising an indication of a segment of the memory array where the data is stored, and determines whether a write temperature associated with the data is stored in a flag byte corresponding to the segment of the memory array. Responsive to determining that the write temperature associated with the data is stored in the flag byte, the control logic determines a cross-temperature for the data based on the write temperature and a read temperature at a time when the request to read the data is received, determines a program/erase cycle count associated with the segment of the memory array, and determines, based on the cross-temperature and the program/erase cycle count, whether to perform a corrective action to calibrate a read voltage level to be applied to the memory array to read the data from the segment.

    On-die cross-temperature management for a memory device
    9.
    发明授权
    On-die cross-temperature management for a memory device 有权

    公开(公告)号：US12067290B2

    公开(公告)日：2024-08-20

    申请号：US17591406

    申请日：2022-02-02

    Applicant: Micron Technology, Inc.

    Inventor： Kishore Kumar Muchherla ,  Violante Moschiano ,  Akira Goda ,  Jeffrey S. McNeil ,  Jung Sheng Hoei ,  Sivagnanam Parthasarathy ,  James Fitzpatrick ,  Patrick R. Khayat

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

    Abstract: Control logic in a memory device receives a request to read data from a memory array of a memory device, the request comprising an indication of a segment of the memory array where the data is stored, and determines whether a write temperature associated with the data is stored in a flag byte corresponding to the segment of the memory array. Responsive to determining that the write temperature associated with the data is stored in the flag byte, the control logic determines a cross-temperature for the data based on the write temperature and a read temperature at a time when the request to read the data is received, determines a program/erase cycle count associated with the segment of the memory array, and determines, based on the cross-temperature and the program/erase cycle count, whether to perform a corrective action to calibrate a read voltage level to be applied to the memory array to read the data from the segment.

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