Apparatus and method for controlling access to memory module

    公开(公告)号:US11487469B2

    公开(公告)日:2022-11-01

    申请号:US16847623

    申请日:2020-04-13

    Abstract: An apparatus controls access to a memory module coupled to a host controller via a data bus to exchange data with the host controller. The apparatus has a configurable information memory and comprises: an access control input port via which the apparatus receives a data access command from the host controller; a control unit to identify a data access command including an access address directed to a predetermined storage region of the memory module, and generate an information processing command based at least on the access address directed to the predetermined storage region, such that the control unit can configure the information memory based on the information processing command or provide the information processing command to the memory module; and an access control output port via which the apparatus provides the information processing command to the memory module, such that the memory module outputs corresponding data information to the host controller based on the information processing command.

    Memory controller and method for accessing memory module

    公开(公告)号:US11226768B2

    公开(公告)日:2022-01-18

    申请号:US15950174

    申请日:2018-04-11

    Abstract: A memory controller and a method for accessing a memory module are provided. The memory controller is coupled between the memory module and a host controller to control the access of the host controller to the memory module. The memory controller comprises: a central buffer coupled to the host controller for receiving a data access command from the host controller, and coupled to the memory module for providing a modified data access command to the memory module; wherein the central buffer comprises an access command processing module, for processing the data access command to generate the modified data access command; and a data buffer coupled to the central buffer for receiving the modified data access command from the central buffer, and coupled between the host controller and the memory module for exchanging data between the host controller and the memory module under the control of the modified data access command.

    Memory controller
    3.
    发明授权

    公开(公告)号:US11157183B2

    公开(公告)日:2021-10-26

    申请号:US16721936

    申请日:2019-12-20

    Abstract: The application discloses a memory controller coupled to a memory module for controlling access to the memory module. The memory controller comprises: a registering clock driver coupled to the memory module for providing a data access command to the memory module so as to control access to the memory module; and a data buffer coupled between the registering clock driver and the memory module for exchanging data between the memory module and the registering clock driver under the control of the registering clock driver; wherein the registering clock driver comprises a computing unit for computing the data received via the data buffer from the memory module and providing a computing result to the memory module via the data buffer.

    Memory controller and method for accessing memory modules and processing sub-modules

    公开(公告)号:US10929029B2

    公开(公告)日:2021-02-23

    申请号:US16239542

    申请日:2019-01-04

    Abstract: A memory controller and a method for accessing a memory module are provided. The memory controller is coupled between the memory module and a host controller to control the access of the host controller to the memory module. The memory controller comprises: a central buffer coupled to the host controller for receiving a data access command from the host controller, and coupled to the memory module for providing a modified data access command to the memory module; wherein the central buffer comprises an access command processing module, for processing the data access command to generate the modified data access command; and a data buffer coupled to the central buffer for receiving the modified data access command from the central buffer, and coupled between the host controller and the memory module for exchanging data between the host controller and the memory module under the control of the modified data access command.

    Data conversion control apparatus, memory device and memory system

    公开(公告)号:US11132313B2

    公开(公告)日:2021-09-28

    申请号:US16881016

    申请日:2020-05-22

    Abstract: A data conversion control apparatus, comprising: at least one first interface each for coupling a first external interface, both of the first interface and the first external interface being in accordance with a predetermined physical interface standard, wherein data transmitted between the first interface and the first external interface is in accordance with a configurable application layer protocol; at least one second interface each for coupling a second external interface, wherein the second external interface is a memory interface in accordance with a predetermined memory interface standard, and the second interface is configurable to match the predetermined memory interface standard; and a data rebuild unit coupled between the at least one first interface and the at least one second interface, wherein the data rebuild unit is configured to rebuild data such that data can be transmitted in respective formats between the at least one first interface and the at least one second interface.

    Memory controller, method for performing access control to memory module

    公开(公告)号:US10983711B2

    公开(公告)日:2021-04-20

    申请号:US15952246

    申请日:2018-04-13

    Abstract: The application discloses a memory controller and a method for controlling an access to a memory module. The memory controller is coupled between the memory module and a host controller to control the access of the host controller to the memory module. The memory controller comprises: a central buffer coupled to the host controller for receiving data access command from the host controller and coupled to the memory module for providing an encrypted data access command to the memory module; wherein the central buffer comprises a command processing module, for performing encryption operation to a data access command with a predefined command encryption algorithm to generate an encrypted data access command; wherein a data channel is coupled between the memory module and the host controller, and wherein under the control of the encrypted data access command, the memory module exchanges data with the host controller via the data channel.

    Memory controller, method for performing access control to memory module

    公开(公告)号:US10936212B2

    公开(公告)日:2021-03-02

    申请号:US16239549

    申请日:2019-01-04

    Abstract: The application discloses a memory controller and a method for controlling an access to a memory module. The memory controller is coupled between the memory module and a host controller to control the access of the host controller to the memory module. The memory controller comprises: a central buffer coupled to the host controller for receiving data access command from the host controller and coupled to the memory module for providing an encrypted data access command to the memory module; wherein the central buffer comprises a command processing module, for performing encryption operation to a data access command with a predefined command encryption algorithm to generate an encrypted data access command; wherein a data channel is coupled between the memory module and the host controller, and wherein under the control of the encrypted data access command, the memory module exchanges data with the host controller via the data channel.

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