公开(公告)号：US07678680B2

公开(公告)日：2010-03-16

申请号：US11144483

申请日：2005-06-02

Applicant: Sven Fuchs ,  Mark Pavier

Inventor： Sven Fuchs ,  Mark Pavier

IPC: H01L21/44

CPC classification number: H01L23/10 ,  H01L23/041 ,  H01L24/02 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/32245 ,  H01L2224/73153 ,  H01L2224/73253 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/13033 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/16152 ,  H01L2924/00

Abstract: A semiconductor device that includes an electrode of one material and a conductive material of lower resistivity formed over the electrode and a process for fabricating the semiconductor device.

Abstract translation: 一种半导体器件，其包括在电极上形成的一种材料的电极和具有较低电阻率的导电材料，以及制造该半导体器件的工艺。

公开(公告)号：US07227198B2

公开(公告)日：2007-06-05

申请号：US11202004

申请日：2005-08-11

Applicant: Mark Pavier ,  Ajit Dubhashi ,  Norman G. Connah ,  Jorge Cerezo

Inventor： Mark Pavier ,  Ajit Dubhashi ,  Norman G. Connah ,  Jorge Cerezo

IPC: H01L31/111 ,  H01L23/495 ,  H01L23/48 ,  H01L23/34

CPC classification number: H01L23/49562 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/37124 ,  H01L2224/37144 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/2075

Abstract: A semiconductor package that includes two power semiconductor dies, such as power MOSFET dies, including vertical conduction MOSFETs, arranged in a half-bridge configuration is disclosed. The package may be mounted on a split conductive pad including two isolated die pads, each die pad being electrically connected to the second power electrode of the die that is on it. The split pad may include several conductive leads, including at least one output lead electrically connected to a first electrode of the first semiconductor die on the same side of the die as the control electrode and to the second electrode of the second die located on the opposite side of the second die from the control electrode.

Abstract translation: 公开了一种半导体封装，其包括以半桥配置布置的两个功率半导体管芯，例如功率MOSFET管芯，包括垂直导通MOSFET。 封装可以安装在包括两个隔离管芯焊盘的分离导电焊盘上，每个管芯焊盘电连接到其上的管芯的第二电源电极。 分离焊盘可以包括几个导电引线，包括至少一个输出引线，其电连接到与控制电极在管芯的同一侧上的第一半导体管芯的第一电极和位于相对的管芯上的第二管芯的第二电极 一侧的第二模具从控制电极。

公开(公告)号：US20070108585A1

公开(公告)日：2007-05-17

申请号：US11595206

申请日：2006-11-10

Applicant: Mark Pavier ,  Andrew Sawle ,  Martin Standing

Inventor： Mark Pavier ,  Andrew Sawle ,  Martin Standing

IPC: H01L23/48

CPC classification number: H01L23/043 ,  H01L21/56 ,  H01L23/142 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/3675 ,  H01L23/3736 ,  H01L23/4334 ,  H01L23/492 ,  H01L23/49562 ,  H01L23/49582 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/19 ,  H01L24/24 ,  H01L24/32 ,  H01L24/37 ,  H01L24/83 ,  H01L24/97 ,  H01L25/07 ,  H01L2224/0346 ,  H01L2224/0508 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/33181 ,  H01L2224/37147 ,  H01L2224/73153 ,  H01L2224/73267 ,  H01L2224/83815 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/0102 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0106 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/40252 ,  H01L2924/403 ,  H01L2924/40407 ,  H01L2224/82 ,  H01L2224/83

Abstract: A semiconductor package that includes a semiconductor die, an insulation around the die, and a conforming conductive pad coupled to an electrode of the die.

Abstract translation: 一种半导体封装，其包括半导体管芯，管芯周围的绝缘体，以及耦合到管芯的电极的一致的导电焊盘。

公开(公告)号：US20070096299A1

公开(公告)日：2007-05-03

申请号：US11590942

申请日：2006-11-01

Applicant: Mark Pavier

Inventor： Mark Pavier

IPC: H01L23/34

CPC classification number: H01L23/4334 ,  H01L23/49575 ,  H01L2224/16 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A multi chip housing has a lead frame to which plural die are soldered. A heat spreader conductive cap encloses a volume containing the plural die or chips and is fixed to the periphery of the lead frame. The tops of the die are closely spaced from the interior of the cap and the volume is filled with a thermally conductive, electrically insulating plastic encapsulant.

Abstract translation: 多芯片壳体具有引导框架，多个管芯被焊接到该引线框架上。 散热器导电盖包围包含多个裸片或芯片的体积并且固定到引线框架的周边。 模具的顶部与盖的内部紧密地间隔开，并且体积填充有导热的，电绝缘的塑料密封剂。

公开(公告)号：US20060033122A1

公开(公告)日：2006-02-16

申请号：US11202004

申请日：2005-08-11

Applicant: Mark Pavier ,  Ajit Dubhashi ,  Norman Connah ,  Jorge Cerezo

Inventor： Mark Pavier ,  Ajit Dubhashi ,  Norman Connah ,  Jorge Cerezo

IPC: H01L31/111

CPC classification number: H01L23/49562 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/37124 ,  H01L2224/37144 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/2075

Abstract: A semiconductor package which includes two power semiconductor die arranged in a half-bridge configuration.

Abstract translation: 一种半导体封装，其包括以半桥配置布置的两个功率半导体芯片。

公开(公告)号：US08466546B2

公开(公告)日：2013-06-18

申请号：US11409298

申请日：2006-04-21

Applicant: Andy Farlow ,  Mark Pavier ,  Andrew N. Sawle ,  George Pearson ,  Martin Standing

Inventor： Andy Farlow ,  Mark Pavier ,  Andrew N. Sawle ,  George Pearson ,  Martin Standing

IPC: H01L23/48

CPC classification number: H01L24/33 ,  H01L23/041 ,  H01L23/492 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/29 ,  H01L2224/29007 ,  H01L2224/291 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29311 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/32245 ,  H01L2224/73153 ,  H01L2224/83801 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/078 ,  H01L2924/0781 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/16152 ,  H01L2924/166 ,  H01L2924/30105 ,  H01L2924/01083 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299

Abstract: A semiconductor package including a conductive clip preferably in the shape of a can, a semiconductor die, and a conductive stack interposed between the die and the interior of the can which includes a conductive platform and a conductive adhesive body.

Abstract translation: 一种半导体封装，其包括优选为罐形状的导电夹子，半导体管芯和插入在所述管芯和所述罐体内部的导电堆叠，其包括导电平台和导电粘合体。

公开(公告)号：US07745930B2

公开(公告)日：2010-06-29

申请号：US11409679

申请日：2006-04-24

Applicant: Norman Glyn Connah ,  Mark Pavier ,  Phillip Adamson ,  Hazel D Schofield

Inventor： Norman Glyn Connah ,  Mark Pavier ,  Phillip Adamson ,  Hazel D Schofield

IPC: H01L23/34

CPC classification number: H01L23/49527 ,  H01L23/15 ,  H01L23/36 ,  H01L23/3735 ,  H01L23/4334 ,  H01L23/492 ,  H01L23/4951 ,  H01L23/49531 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49844 ,  H01L23/49861 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/0603 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/48644 ,  H01L2224/48744 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/73255 ,  H01L2224/85207 ,  H01L2224/85444 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/30107 ,  H03K17/567 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device package includes a substrate with one or more pads and at least one semiconductor device that has one or more of its electrodes electrically connected to the substrate pads. The package also includes one or more terminals in electrical connection with the substrate pads and that provide for external connection to the device.

Abstract translation: 半导体器件封装包括具有一个或多个焊盘的衬底和至少一个半导体器件，其具有电连接到衬底焊盘的一个或多个电极。 封装还包括与衬底焊盘电连接的一个或多个端子，并且提供与设备的外部连接。

公开(公告)号：US07547964B2

公开(公告)日：2009-06-16

申请号：US11410457

申请日：2006-04-24

Applicant: Mark Pavier ,  Norman Glyn Connah

Inventor： Mark Pavier ,  Norman Glyn Connah

IPC: H01L23/52

CPC classification number: H01L23/49527 ,  H01L23/15 ,  H01L23/36 ,  H01L23/3735 ,  H01L23/4334 ,  H01L23/492 ,  H01L23/4951 ,  H01L23/49531 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49844 ,  H01L23/49861 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/0603 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/48644 ,  H01L2224/48744 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/73255 ,  H01L2224/85207 ,  H01L2224/85444 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/30107 ,  H03K17/567 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device package includes a die pad, a substrate disposed on the die pad, and a III-nitride based semiconductor device disposed on the substrate. The device package may also include a second semiconductor device disposed on the die pad or the substrate, which device may be electrically connected to the III-nitride based device to form a circuit.

Abstract translation: 半导体器件封装包括管芯焊盘，设置在管芯焊盘上的衬底以及设置在衬底上的III族氮化物基半导体器件。 器件封装还可以包括设置在管芯焊盘或衬底上的第二半导体器件，该器件可以电连接到基于III族氮化物的器件以形成电路。

公开(公告)号：US20080017987A1

公开(公告)日：2008-01-24

申请号：US11890965

申请日：2007-08-08

Applicant: Sven Fuchs ,  Mark Pavier

Inventor： Sven Fuchs ,  Mark Pavier

IPC: H01L23/482

CPC classification number: H01L24/30 ,  H01L23/3107 ,  H01L23/498 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/2908 ,  H01L2224/29124 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29166 ,  H01L2224/30505 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73153 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/0132 ,  H01L2924/01327 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0483 ,  H01L2924/1203 ,  H01L2924/12042 ,  H01L2924/13033 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19043 ,  H01L2924/3651 ,  H01L2924/00

Abstract: A semiconductor device that includes an electrode of one material and a conductive material of lower resistivity formed over the electrode and a process for fabricating the semiconductor device.

Abstract translation: 一种半导体器件，其包括在电极上形成的一种材料的电极和具有较低电阻率的导电材料，以及制造该半导体器件的工艺。

公开(公告)号：US20070096270A1

公开(公告)日：2007-05-03

申请号：US11591835

申请日：2006-11-02

Applicant: Mark Pavier

Inventor： Mark Pavier

IPC: H01L23/495

CPC classification number: H01L23/49575 ,  H01L23/4334 ,  H01L23/49562 ,  H01L24/81 ,  H01L2224/16245 ,  H01L2224/73253 ,  H01L2224/81801 ,  H01L2924/10253 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/16152 ,  H01L2924/19105 ,  H01L2924/00

Abstract: A multi chip housing has a lead frame to which plural die are soldered. A heat spreader conductive cap encloses a volume containing the plural die or chips and is fixed to the periphery of the lead frame. The die may be silicon or GaN based MOSFETs or integrated circuits or a mixture thereof. The tops of the die are closely spaced from the interior of the cap and the volume is filled with a thermally conductive, electrically insulating plastic encapsulant. One die can be connected to the clip as well as the lead frame and the other may be an IC die insulated from the clip.

Abstract translation: 多芯片壳体具有引导框架，多个管芯被焊接到该引线框架上。 散热器导电盖包围包含多个裸片或芯片的体积并且固定到引线框架的周边。 芯片可以是硅或GaN基MOSFET或集成电路或其混合物。 模具的顶部与盖的内部紧密地间隔开，并且体积填充有导热的，电绝缘的塑料密封剂。 一个管芯可以连接到夹子以及引线框架，另一个管芯可以是与夹子绝缘的IC管芯。