公开(公告)号：US20180226980A1

公开(公告)日：2018-08-09

申请号：US15949395

申请日：2018-04-10

Applicant: MaxLinear, Inc.

Inventor： Gaurav Chandra ,  Tao Zeng ,  Shantha Murthy Prem Swaroop

IPC: H03M1/06 ,  H03M1/10 ,  H03M1/66

CPC classification number: H03M1/066 ,  H03M1/1038 ,  H03M1/66

Abstract: Systems and methods are provided for managing dynamic element matching (DEM) in digital-to-analog converters (DACs). One or more parameters associated with the DAC and/or a signal being converted via the DAC; and based on the one or more parameters, conditions affecting dynamic element matching in the DAC may be assessed. Based on the assessing of the conditions, one or more adjustments may be determined and dynamically applied to the dynamic element matching in the DAC.

公开(公告)号：US09991899B2

公开(公告)日：2018-06-05

申请号：US15790343

申请日：2017-10-23

Applicant: MaxLinear, Inc.

Inventor： Gaurav Chandra ,  Tao Zeng ,  Shantha Murthy Prem Swaroop ,  Jianyu Zhu

IPC: H03M1/66 ,  H03M1/06

CPC classification number: H03M1/0624 ,  H03M1/66

Abstract: Systems and methods are provided for adaptive configuration and control of digital-to-analog converters (DACs). Performance of a plurality of conversion elements in a digital-to-analog converter (DAC) may be assessed based on particular input conditions associated with a digital input to the DAC, and the DAC may be configured based on the assessing of performance. Each conversion element of the plurality of conversion elements handles a particular bit in the digital input. The configuring may comprise selecting a subset of the plurality of conversion elements, and setting only the subset of the plurality of conversion elements to apply a particular type of operations. The particular type of operations pertains to applying digital-to-analog conversions via the DAC, and the particular type of operations relates to or affects performance. The particular input conditions may comprise signal backoff.

公开(公告)号：US09800254B2

公开(公告)日：2017-10-24

申请号：US15130602

申请日：2016-04-15

Applicant: MaxLinear, Inc.

Inventor： Gaurav Chandra ,  Tao Zeng ,  Shantha Murthy Prem Swaroop ,  Jianyu Zhu

IPC: H03M1/66 ,  H03M1/06

CPC classification number: H03M1/0624 ,  H03M1/66

Abstract: Systems and methods are provided for digital-to-analog converter (DAC) with partial constant switching. A digital-to-analog converter (DAC) comprising a plurality of conversion elements may be configured to apply constant switching in only some of the conversion elements. Only conversion elements applying constant switching may incorporate circuitry for providing such the constant switching. Alternatively, each conversion element may incorporate constant switching circuitry and functionality, and the constant switching may then be turned on or off for each conversion element adaptively, such as based on input conditions.

公开(公告)号：US20160308547A1

公开(公告)日：2016-10-20

申请号：US15130636

申请日：2016-04-15

Applicant: MaxLinear, Inc.

Inventor： Gaurav Chandra ,  Tao Zeng ,  Shantha Murthy Prem Swaroop ,  Jianyu Zhu

IPC: H03M1/10 ,  H03M1/68

CPC classification number: H03M1/1023 ,  H03M1/0607 ,  H03M1/68

Abstract: Systems and methods are provided for digital-to-analog converter (DAC) with digital offsets. A digital offset may be applied to an input of a digital-to-analog converter (DAC), and digital-to-analog conversions are then applied via the DAC to the input with the digital offset. The digital offset is set to account for one or more conditions relating to inputs to the DAC, with the one or more conditions affect switching characteristics of one or more of a plurality of conversion elements in the DAC, and where each conversion element handles a particular bit in inputs to the DAC. The digital offset may be determined dynamically and adaptively, such as based on the input and/or conditions relating to the input. Alternatively, the digital offset may be pre-determined and fixed. One or more adjustments may be selectively applied to the digital offset for particular input conditions.

Abstract translation: 为具有数字偏移量的数模转换器（DAC）提供了系统和方法。 数字偏移可以应用于数模转换器（DAC）的输入端，然后通过DAC将数模转换应用于具有数字偏移量的输入。 数字偏移被设置为考虑与DAC的输入相关的一个或多个条件，其中一个或多个条件影响DAC中的多个转换元件中的一个或多个的开关特性，并且其中每个转换元件处理特定 位到DAC的输入。 数字偏移可以被动态地和自适应地确定，例如基于与输入有关的输入和/或条件。 或者，数字偏移可以是预定的和固定的。 一个或多个调整可以选择性地应用于特定输入条件的数字偏移。

公开(公告)号：US09154154B2

公开(公告)日：2015-10-06

申请号：US14471587

申请日：2014-08-28

Applicant: Maxlinear, Inc.

Inventor： Rajesh Zele ,  Gaurav Chandra

IPC: H03M1/66 ,  H03M1/70

CPC classification number: H03M1/66 ,  H03F3/45192 ,  H03F2203/45526 ,  H03M1/70 ,  H03M1/742

Abstract: Methods and systems for a low input voltage low impedance termination stage for current inputs may include, in a semiconductor die, generating an output current proportional to an input signal, where the output current is generated by an output stage that may include a pair of input cascode transistors and at least one pair of stacked output transistors. A source-follower feedback path for the input cascode transistors may include a feedback transistor with its gate terminal coupled to a drain terminal of a first of the input cascode transistors, a drain of the feedback transistor coupled to a supply voltage, and a source terminal of the feedback transistor coupled to a current source that is coupled to ground. A current source may be coupled to the drain of the first of the input cascode transistors. The supply voltage may be coupled to the stacked output transistors via a load resistor.

Abstract translation: 用于电流输入的低输入电压低阻抗终端级的方法和系统可以包括在半导体管芯中产生与输入信号成比例的输出电流，其中输出电流由输出级产生，输出级可包括一对输入 共源共栅晶体管和至少一对堆叠输出晶体管。 用于输入共源共栅晶体管的源极 - 跟随器反馈路径可以包括其栅极端子耦合到输入共源共栅晶体管中的第一个的漏极端子的反馈晶体管，耦合到电源电压的反馈晶体管的漏极和源极端子 耦合到耦合到地的电流源的反馈晶体管。 电流源可以耦合到第一输入共源共栅晶体管的漏极。 电源电压可以经由负载电阻器耦合到堆叠的输出晶体管。

公开(公告)号：US20190115929A1

公开(公告)日：2019-04-18

申请号：US16217348

申请日：2018-12-12

Applicant: Maxlinear, Inc.

Inventor： Gaurav Chandra ,  Tao Zeng ,  Shantha Murthy Prem Swaroop ,  Jianyu Zhu

IPC: H03M1/06

CPC classification number: H03M1/0624 ,  H03M1/66

Abstract: A digital-to-analog converter (DAC) controller system may be configured for controlling switching in an associated digital-to-analog converter (DAC), based on a plurality of system inputs that include at least a first system input corresponding to an input applied to the DAC for controlling switching therein, and a second system input that includes a reference control signal. The DAC controller system may include a logic gate circuit that generates a gate output based on two gate inputs that include the first system input and an input set based on the second system input; and a plurality of timing circuits that generate timing outputs for controlling timing of switching in the DAC, which include at least one timing circuit that generates a timing output based on the gate output, with the timing output configured for application in conjunction with and for adjusting a timing output of another timing circuit.

公开(公告)号：US09692435B2

公开(公告)日：2017-06-27

申请号：US15130636

申请日：2016-04-15

Applicant: MaxLinear, Inc.

Inventor： Gaurav Chandra ,  Tao Zeng ,  Shantha Murthy Prem Swaroop ,  Jianyu Zhu

IPC: H03M1/10 ,  H03M1/06 ,  H03M1/68

CPC classification number: H03M1/1023 ,  H03M1/0607 ,  H03M1/68

Abstract: Systems and methods are provided for digital-to-analog converter (DAC) with digital offsets. A digital offset may be applied to an input of a digital-to-analog converter (DAC), and digital-to-analog conversions are then applied via the DAC to the input with the digital offset. The digital offset is set to account for one or more conditions relating to inputs to the DAC, with the one or more conditions affect switching characteristics of one or more of a plurality of conversion elements in the DAC, and where each conversion element handles a particular bit in inputs to the DAC. The digital offset may be determined dynamically and adaptively, such as based on the input and/or conditions relating to the input. Alternatively, the digital offset may be pre-determined and fixed. One or more adjustments may be selectively applied to the digital offset for particular input conditions.

公开(公告)号：US09397686B2

公开(公告)日：2016-07-19

申请号：US14865582

申请日：2015-09-25

Applicant: Maxlinear, Inc.

Inventor： Rajesh Zele ,  Gaurav Chandra

IPC: H03M1/66 ,  H03M1/70 ,  H03F3/45 ,  H03M1/74

CPC classification number: H03M1/66 ,  H03F3/45192 ,  H03F2203/45526 ,  H03M1/70 ,  H03M1/742

Abstract: A low input voltage low impedance termination stage for current inputs may include an output stage for an electrical circuit, the output stage including input cascode transistors and stacked output transistors. A source-follower feedback path for the input cascode transistors may include a feedback transistor with its gate terminal coupled to a drain terminal of a first of the input cascode transistors, a drain of the feedback transistor coupled to a supply voltage, and a source terminal of the feedback transistor coupled to a current source. A current source may be coupled to the drain of the first of the input cascode transistors. The supply voltage may be coupled to the stacked output transistors via a load resistor. The input cascode transistors, the feedback transistor, and the stacked output transistors may include complementary metal-oxide semiconductor (CMOS) transistors.

Abstract translation: 用于电流输入的低输入电压低阻抗终端级可以包括用于电路的输出级，输出级包括输入共源共栅晶体管和堆叠输出晶体管。 用于输入共源共栅晶体管的源极 - 跟随器反馈路径可以包括其栅极端子耦合到输入共源共栅晶体管中的第一个的漏极端子的反馈晶体管，耦合到电源电压的反馈晶体管的漏极和源极端子 耦合到电流源的反馈晶体管。 电流源可以耦合到第一输入共源共栅晶体管的漏极。 电源电压可以经由负载电阻器耦合到堆叠的输出晶体管。 输入共源共栅晶体管，反馈晶体管和堆叠输出晶体管可以包括互补金属氧化物半导体（CMOS）晶体管。

公开(公告)号：US20160020780A1

公开(公告)日：2016-01-21

申请号：US14865582

申请日：2015-09-25

Applicant: Maxlinear, Inc.

Inventor： Rajesh Zele ,  Gaurav Chandra

IPC: H03M1/66

CPC classification number: H03M1/66 ,  H03F3/45192 ,  H03F2203/45526 ,  H03M1/70 ,  H03M1/742

Abstract: A low input voltage low impedance termination stage for current inputs is disclosed and may include an output stage for an electrical circuit, the output stage including input cascode transistors and stacked output transistors, wherein a source-follower feedback path for the input cascode transistors may include a feedback transistor with its gate terminal coupled to a drain terminal of a first of the input cascode transistors, a drain of the feedback transistor coupled to a supply voltage, and a source terminal of the feedback transistor coupled to a current source. A current source may be coupled to the drain of the first of the input cascode transistors. The supply voltage may be coupled to the stacked output transistors via a load resistor. The input cascode transistors, the feedback transistor, and the stacked output transistors may include complementary metal-oxide semiconductor (CMOS) transistors.

Abstract translation: 公开了用于电流输入的低输入电压低阻抗终端级，并且可以包括用于电路的输出级，输出级包括输入共源共栅晶体管和堆叠输出晶体管，其中用于输入共源共栅晶体管的源极 - 跟随器反馈路径可以包括 反馈晶体管，其栅极端子耦合到输入共源共栅晶体管中的第一个的漏极端子，耦合到电源电压的反馈晶体管的漏极和耦合到电流源的反馈晶体管的源极端子。 电流源可以耦合到第一输入共源共栅晶体管的漏极。 电源电压可以经由负载电阻器耦合到堆叠的输出晶体管。 输入共源共栅晶体管，反馈晶体管和堆叠输出晶体管可以包括互补金属氧化物半导体（CMOS）晶体管。

公开(公告)号：US20150061910A1

公开(公告)日：2015-03-05

申请号：US14471587

申请日：2014-08-28

Applicant: Maxlinear, Inc.

Inventor： Rajesh Zele ,  Gaurav Chandra

IPC: H03M1/70

CPC classification number: H03M1/66 ,  H03F3/45192 ,  H03F2203/45526 ,  H03M1/70 ,  H03M1/742

Abstract: Methods and systems for a low input voltage low impedance termination stage for current inputs may comprise, in a semiconductor die, generating an output current proportional to an input signal, where the output current is generated by an output stage that may include a pair of input cascode transistors and at least one pair of stacked output transistors. A source-follower feedback path for the input cascode transistors may include a feedback transistor with its gate terminal coupled to a drain terminal of a first of the input cascode transistors, a drain of the feedback transistor coupled to a supply voltage, and a source terminal of the feedback transistor coupled to a current source that is coupled to ground. A current source may be coupled to the drain of the first of the input cascode transistors. The supply voltage may be coupled to the stacked output transistors via a load resistor.

Abstract translation: 用于电流输入的用于低输入电压低阻抗终止级的方法和系统可包括在半导体管芯中产生与输入信号成比例的输出电流，其中输出电流由输出级产生，输出级可包括一对输入 共源共栅晶体管和至少一对堆叠输出晶体管。 用于输入共源共栅晶体管的源极跟随器反馈路径可以包括反馈晶体管，其栅极端子耦合到输入共源共栅晶体管中的第一个的漏极端子，耦合到电源电压的反馈晶体管的漏极和源极端子 耦合到耦合到地的电流源的反馈晶体管。 电流源可以耦合到第一输入共源共栅晶体管的漏极。 电源电压可以经由负载电阻器耦合到堆叠的输出晶体管。