公开(公告)号：US20190139584A1

公开(公告)日：2019-05-09

申请号：US16237396

申请日：2018-12-31

Applicant: Maxlinear, Inc.

Inventor： Curtis Ling ,  Vadim Smolyakov ,  Timothy Gallagher ,  Glenn Gulak

IPC: G11C5/14 ,  G06F11/10 ,  G11C29/02

Abstract: A method and apparatus for memory power and/or area reduction. An array of memory cells may be scanned to detect faulty memory cells, if any, in the array. A supply voltage Vmem applied to the array of memory cells may be controlled based on a result of the scan, and based on a sensitivity coefficient of one, or more, of the array of memory cells. The sensitivity coefficient may indicate an impact that the one, or more, of the array of memory cells being faulty may have on the performance of a device that reads and writes data to the memory array. Additionally or alternatively, the physical dimensions of the memory cells may be determined based on the sensitivity coefficient(s) and/or based on a number of faulty memory cells that can be tolerated in the array of memory cells.

公开(公告)号：US10176850B2

公开(公告)日：2019-01-08

申请号：US15880913

申请日：2018-01-26

Applicant: Maxlinear, Inc.

Inventor： Curtis Ling ,  Vadim Smolyakov ,  Timothy Gallagher ,  Glenn Gulak

IPC: G11C5/14 ,  G11C29/02 ,  G06F11/10 ,  G11C29/04

Abstract: A method and apparatus for memory power and/or area reduction. An array of memory cells may be scanned to detect faulty memory cells, if any, in the array. A supply voltage Vmem applied to the array of memory cells may be controlled based on a result of the scan, and based on a sensitivity coefficient of one, or more, of the array of memory cells. The sensitivity coefficient may indicate an impact that the one, or more, of the array of memory cells being faulty may have on the performance of a device that reads and writes data to the memory array. Additionally or alternatively, the physical dimensions of the memory cells may be determined based on the sensitivity coefficient(s) and/or based on a number of faulty memory cells that can be tolerated in the array of memory cells.

公开(公告)号：US10374633B2

公开(公告)日：2019-08-06

申请号：US15619764

申请日：2017-06-12

Applicant: Maxlinear, Inc.

Inventor： Mario Milicevic ,  Glenn Gulak

IPC: H03M13/11 ,  H03M13/37 ,  H03M13/00 ,  H03M13/53

Abstract: A Low-Density Parity-Check (LDPC) decoder and a method for LDPC decoding are provided. The LDPC decoder receives a soft-decision input codeword block in which the probability of a bit being a “0” or a “1” is represented as a log-likelihood ratio (LLR). During LDPC decoding, a sequence of hardware logic units iteratively updates the soft-decision input codeword block until a valid codeword is found or a maximum number of decoding iterations is reached. Each hardware logic unit comprises a check node (CN) update logic unit and a variable node (VN) update logic unit. The CN update logic units are coupled via a closed CN path, and the VN update logic units are coupled via a closed VN path. Aspects of this LDPC decoder alleviate the global routing and energy efficiency challenges of traditional LDPC decoders, to enable multi-rate, multi-Gb/s decoding without compromising error correction performance in next-generation systems and future CMOS technology nodes.

公开(公告)号：US20180013446A1

公开(公告)日：2018-01-11

申请号：US15619764

申请日：2017-06-12

Applicant: Maxlinear, Inc.

Inventor： Mario Milicevic ,  Glenn Gulak

IPC: H03M13/11 ,  H03M13/37

CPC classification number: H03M13/1174 ,  H03M13/112 ,  H03M13/1122 ,  H03M13/1128 ,  H03M13/114 ,  H03M13/116 ,  H03M13/3746 ,  H03M13/635 ,  H03M13/6502 ,  H03M13/6505 ,  H03M13/6516

Abstract: A Low-Density Parity-Check (LDPC) decoder and a method for LDPC decoding are provided. The LDPC decoder receives a soft-decision input codeword block in which the probability of a bit being a “0” or a “1” is represented as a log-likelihood ratio (LLR). During LDPC decoding, a sequence of hardware logic units iteratively updates the soft-decision input codeword block until a valid codeword is found or a maximum number of decoding iterations is reached. Each hardware logic unit comprises a check node (CN) update logic unit and a variable node (VN) update logic unit. The CN update logic units are coupled via a closed CN path, and the VN update logic units are coupled via a closed VN path. Aspects of this LDPC decoder alleviate the global routing and energy efficiency challenges of traditional LDPC decoders, to enable multi-rate, multi-Gb/s decoding without compromising error correction performance in next-generation systems and future CMOS technology nodes.

公开(公告)号：US09576614B2

公开(公告)日：2017-02-21

申请号：US14450324

申请日：2014-08-04

Applicant: MaxLinear, Inc.

Inventor： Curtis Ling ,  Vadim Smolyakov ,  Timothy Gallagher ,  Glenn Gulak

IPC: G11C5/14 ,  G11C29/02 ,  G06F11/10 ,  G11C29/04

CPC classification number: G11C5/144 ,  G06F11/1048 ,  G11C5/14 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0409

Abstract: A method and apparatus for memory power and/or area reduction. An array of memory cells may be scanned to detect faulty memory cells, if any, in the array. A supply voltage Vmem applied to the array of memory cells may be controlled based on a result of the scan, and based on a sensitivity coefficient of one, or more, of the array of memory cells. The sensitivity coefficient may indicate an impact that the one, or more, of the array of memory cells being faulty may have on the performance of a device that reads and writes data to the memory array. Additionally or alternatively, the physical dimensions of the memory cells may be determined based on the sensitivity coefficient(s) and/or based on a number of faulty memory cells that can be tolerated in the array of memory cells.

Abstract translation: 一种用于存储器功率和/或面积减小的方法和装置。 可以扫描存储器单元阵列以检测阵列中的故障存储器单元（如果有的话）。 可以基于扫描的结果并且基于存储器单元阵列中的一个或多个的灵敏度系数来控制施加到存储器单元阵列的电源电压Vmem。 灵敏度系数可以指示存储器单元阵列中的一个或多个存在故障的影响可能对于将数据读取和写入存储器阵列的设备的性能有影响。 附加地或替代地，存储器单元的物理尺寸可以基于灵敏度系数和/或基于可以在存储器单元阵列中容忍的故障存储器单元的数量来确定。

公开(公告)号：US09881653B2

公开(公告)日：2018-01-30

申请号：US15434715

申请日：2017-02-16

Applicant: Maxlinear, Inc.

Inventor： Curtis Ling ,  Vadim Smolyakov ,  Timothy Gallagher ,  Glenn Gulak

IPC: G11C5/14 ,  G11C29/02 ,  G11C29/04

CPC classification number: G11C5/144 ,  G06F11/1048 ,  G11C5/14 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0409

Abstract: A method and apparatus for memory power and/or area reduction. An array of memory cells may be scanned to detect faulty memory cells, if any, in the array. A supply voltage Vmem applied to the array of memory cells may be controlled based on a result of the scan, and based on a sensitivity coefficient of one, or more, of the array of memory cells. The sensitivity coefficient may indicate an impact that the one, or more, of the array of memory cells being faulty may have on the performance of a device that reads and writes data to the memory array. Additionally or alternatively, the physical dimensions of the memory cells may be determined based on the sensitivity coefficient(s) and/or based on a number of faulty memory cells that can be tolerated in the array of memory cells.

公开(公告)号：US09337911B2

公开(公告)日：2016-05-10

申请号：US14158546

申请日：2014-01-17

Applicant: MaxLinear, Inc.

Inventor： Dimpesh Patel ,  Mahdi Shabany ,  Glenn Gulak

IPC: H04B7/04 ,  H04L25/03

CPC classification number: H04B7/0456 ,  H04L25/03203

Abstract: An approach for Soft-output K-Best MIMO detection comprises computing an estimated symbol vector and Log-Likelihood Ratio (LLR) values for transmitted bits. The approach includes a relevant discarded paths selection process, a last-stage on-demand expansion process, and a relaxed LLR computation process. The relevant discarded paths selection process includes analyzing the K-Best paths and discarded paths at each intermediate tree level and selecting only those discarded paths for further processing that will help in LLR computation for at least one of the transmitted bits. The last-stage on-demand expansion process includes expanding K paths at the tree level 2NT−1 (NT=number of transmit antennas) on-demand to only 2K−1 lowest Partial Euclidean Distance (PED) paths at last tree level 2NT. The relaxed LLR computation scheme includes approximating LLR computations by assuming that discarded path PED is greater than or equal K-Best path PED.

Abstract translation: 用于软输出K-Best MIMO检测的方法包括计算用于发送位的估计符号向量和对数似然比（LLR）值。 该方法包括相关的丢弃路径选择过程，最后一阶段按需扩展过程以及松弛的LLR计算过程。 相关丢弃路径选择过程包括分析每个中间树级别的K-Best路径和丢弃路径，并且仅选择那些被丢弃的路径用于进一步处理，这将有助于至少一个发送位的LLR计算。 最后阶段的按需扩展过程包括根据需要在树级别2NT-1（NT =发射天线的数量）上将K路径扩展到最后树级别2NT处的仅2K-1最小部分欧几里德距离（PED）路径。 松弛的LLR计算方案包括通过假设丢弃的路径PED大于或等于K-最佳路径PED来近似LLR计算。

公开(公告)号：US20180151202A1

公开(公告)日：2018-05-31

申请号：US15880913

申请日：2018-01-26

Applicant: Maxlinear, Inc.

Inventor： Curtis Ling ,  Vadim Smolyakov ,  Timothy Gallagher ,  Glenn Gulak

IPC: G11C5/14 ,  G11C29/02 ,  G11C29/04

CPC classification number: G11C5/144 ,  G06F11/1048 ,  G11C5/14 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0409

Abstract: A method and apparatus for memory power and/or area reduction. An array of memory cells may be scanned to detect faulty memory cells, if any, in the array. A supply voltage Vmem applied to the array of memory cells may be controlled based on a result of the scan, and based on a sensitivity coefficient of one, or more, of the array of memory cells. The sensitivity coefficient may indicate an impact that the one, or more, of the array of memory cells being faulty may have on the performance of a device that reads and writes data to the memory array. Additionally or alternatively, the physical dimensions of the memory cells may be determined based on the sensitivity coefficient(s) and/or based on a number of faulty memory cells that can be tolerated in the array of memory cells.

公开(公告)号：US20170162233A1

公开(公告)日：2017-06-08

申请号：US15434715

申请日：2017-02-16

Applicant: Maxlinear, Inc.

Inventor： Curtis Ling ,  Vadim Smolyakov ,  Timothy Gallagher ,  Glenn Gulak

IPC: G11C5/14 ,  G11C29/02

CPC classification number: G11C5/144 ,  G06F11/1048 ,  G11C5/14 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0409

Abstract: A method and apparatus for memory power and/or area reduction. An array of memory cells may be scanned to detect faulty memory cells, if any, in the array. A supply voltage Vmem applied to the array of memory cells may be controlled based on a result of the scan, and based on a sensitivity coefficient of one, or more, of the array of memory cells. The sensitivity coefficient may indicate an impact that the one, or more, of the array of memory cells being faulty may have on the performance of a device that reads and writes data to the memory array. Additionally or alternatively, the physical dimensions of the memory cells may be determined based on the sensitivity coefficient(s) and/or based on a number of faulty memory cells that can be tolerated in the array of memory cells.

公开(公告)号：US20150023122A1

公开(公告)日：2015-01-22

申请号：US14450324

申请日：2014-08-04

Applicant: MaxLinear, Inc.

Inventor： Curtis Ling ,  Vadim Smolyakov ,  Timothy Gallagher ,  Glenn Gulak

IPC: G11C5/14

CPC classification number: G11C5/144 ,  G06F11/1048 ,  G11C5/14 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0409

Abstract: A method and apparatus for memory power and/or area reduction. An array of memory cells may be scanned to detect faulty memory cells, if any, in the array. A supply voltage Vmem applied to the array of memory cells may be controlled based on a result of the scan, and based on a sensitivity coefficient of one, or more, of the array of memory cells. The sensitivity coefficient may indicate an impact that the one, or more, of the array of memory cells being faulty may have on the performance of a device that reads and writes data to the memory array. Additionally or alternatively, the physical dimensions of the memory cells may be determined based on the sensitivity coefficient(s) and/or based on a number of faulty memory cells that can be tolerated in the array of memory cells.

Abstract translation: 一种用于存储器功率和/或面积减小的方法和装置。 可以扫描存储器单元阵列以检测阵列中的故障存储器单元（如果有的话）。 可以基于扫描的结果并且基于存储器单元阵列中的一个或多个的灵敏度系数来控制施加到存储器单元阵列的电源电压Vmem。 灵敏度系数可以指示存储器单元阵列中的一个或多个存在故障的影响可能对于将数据读取和写入存储器阵列的设备的性能有影响。 附加地或替代地，存储器单元的物理尺寸可以基于灵敏度系数和/或基于可以在存储器单元阵列中容忍的故障存储器单元的数量来确定。