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公开(公告)号：US08934590B2
公开(公告)日：2015-01-13
申请号：US14107212
申请日：2013-12-16
Applicant: MaxLinear, Inc.
Inventor： Jianyu Zhu , Sheng-Yu Peng , Rodney Chandler , Pawan Tiwari , Rahul Bhatia , Eric Fogleman
CPC classification number: H04L7/0334 , H03M1/1215 , H03M1/1245
Abstract: A signal receiver may comprise a first sampling circuitry that is operable to sample in a first level at a particular main sampling rate; a second sampling circuitry that is operable to sample in a second level, an output of the first sampling circuitry, at a second sampling rate that is reduced compared to the main sampling rate; a third sampling circuitry that is operable to sample in a third level, one or more outputs of the second sampling circuitry, at a third sampling rate that is reduced compared to the second sampling rate; and an analog-to-digital conversion (ADC) circuitry for applying analog-to-digital conversion to one or more outputs of the third sampling circuitry.
Abstract translation: 信号接收器可以包括第一采样电路，其可操作以在特定主采样率下以第一电平进行采样; 第二采样电路，其可操作以以与主采样率相比减小的第二采样率在第二电平中采样第一采样电路的输出; 第三采样电路，其可操作以以与第二采样率相比减小的第三采样率在第三电平，第二采样电路的一个或多个输出中采样; 以及用于将模数转换应用于第三采样电路的一个或多个输出的模数转换（ADC）电路。
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公开(公告)号：US20170272234A1
公开(公告)日：2017-09-21
申请号：US15419063
申请日：2017-01-30
Applicant: MaxLinear, Inc.
Inventor： Jianyu Zhu , Sheng-Yu Peng , Rodney Chandler , Pawan Tiwari , Rahul Bhatia , Eric Fogleman
IPC: H04L7/033
CPC classification number: H04L7/0334 , H03M1/1215 , H03M1/1245
Abstract: A radio frequency (RF) receiver may comprise a first sampling module that is operable to sample in a first level at a particular main sampling rate; a plurality of second-level sampling modules, wherein each of the plurality of second-level sampling modules is operable to sample in a second level, an output of the first level, at a second sampling rate that is reduced compared to the main sampling rate; and a plurality of third-level modules, each comprising a plurality of third-stage sampling sub-modules that are operable to sample at a third sampling rate that is reduced compared to the second sampling rate, and a plurality of corresponding analog-to-digital conversion (ADC) sub-modules.
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Patent Agency Ranking
公开(公告)号：US20150092899A1
公开(公告)日：2015-04-02
申请号：US14563476
申请日：2014-12-08
Applicant: MaxLinear, Inc.
Inventor： Jianyu Zhu , Sheng-Yu Peng , Rodney Chandler , Pawan Tiwari , Rahul Bhatia , Eric Fogleman
IPC: H04L7/033
CPC classification number: H04L7/0334 , H03M1/1215 , H03M1/1245
Abstract: A signal receiver may comprise circuitry for applying multi-level sampling to an input signal, using a plurality of sampling rates that comprises at least two different sampling rates, and circuitry for processing one or more outputs of the multi-level sampling. The processing may comprises sampling at a sampling rate that is different than each of the plurality of sampling rates used during the multi-level sampling and applying analog-to-digital conversion. At least one of the sampling rates used during the multi-level sampling and/or the sampling rate used during the processing may be set based on configuring of one or more clock signals used during the multi-level sampling and/or during the processing. At least one of the one or more clock signals may be configured based on reduction of frequency of a corresponding base clock signal.
Abstract translation: 信号接收机可以包括用于使用包括至少两个不同采样速率的多个采样速率以及用于处理多电平采样的一个或多个输出的电路将多电平采样应用于输入信号的电路。 处理可以包括以与在多级采样期间使用的多个采样率中的每一个不同的采样率进行采样并且应用模数转换。 在处理期间使用的多级采样和/或采样率期间使用的采样率中的至少一个可以基于在多级采样期间和/或处理期间使用的一个或多个时钟信号的配置来设置。 可以基于对应的基本时钟信号的频率的降低来配置一个或多个时钟信号中的至少一个。
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公开(公告)号：US20180278408A1
公开(公告)日：2018-09-27
申请号：US15991488
申请日：2018-05-29
Applicant: MaxLinear, Inc.
Inventor： Jianyu Zhu , Sheng-Yu Peng , Rodney Chandler , Pawan Tiwari , Rahul Bhatia , Eric Fogleman
CPC classification number: H04L7/0334 , H03M1/1215 , H03M1/1245
Abstract: A radio frequency (RF) receiver may comprise a first sampling module that is operable to sample in a first level at a particular main sampling rate; a plurality of second-level sampling modules, wherein each of the plurality of second-level sampling modules is operable to sample in a second level, an output of the first level, at a second sampling rate that is reduced compared to the main sampling rate; and a plurality of third-level modules, each comprising a plurality of third-stage sampling sub-modules that are operable to sample at a third sampling rate that is reduced compared to the second sampling rate, and a plurality of corresponding analog-to-digital conversion (ADC) sub-modules.
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公开(公告)号：US20140105339A1
公开(公告)日：2014-04-17
申请号：US14107212
申请日：2013-12-16
Applicant: MaxLinear, Inc.
Inventor： Jianyu Zhu , Sheng-Yu Peng , Rodney Chandler , Pawan Tiwari , Rahul Bhatia , Eric Fogleman
IPC: H04L7/033
CPC classification number: H04L7/0334 , H03M1/1215 , H03M1/1245
Abstract: A signal receiver may comprise a first sampling circuitry that is operable to sample in a first level at a particular main sampling rate; a second sampling circuitry that is operable to sample in a second level, an output of the first sampling circuitry, at a second sampling rate that is reduced compared to the main sampling rate; a third sampling circuitry that is operable to sample in a third level, one or more outputs of the second sampling circuitry, at a third sampling rate that is reduced compared to the second sampling rate; and an analog-to-digital conversion (ADC) circuitry for applying analog-to-digital conversion to one or more outputs of the third sampling circuitry.
Abstract translation: 信号接收器可以包括第一采样电路，其可操作以在特定主采样率下以第一电平进行采样; 第二采样电路，其可操作以以与主采样率相比减小的第二采样率在第二电平中采样第一采样电路的输出; 第三采样电路，其可操作以以与第二采样率相比减小的第三采样率在第三电平，第二采样电路的一个或多个输出中采样; 以及用于将模数转换应用于第三采样电路的一个或多个输出的模数转换（ADC）电路。
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公开(公告)号：US09985777B2
公开(公告)日：2018-05-29
申请号：US15419063
申请日：2017-01-30
Applicant: MaxLinear, Inc.
Inventor： Jianyu Zhu , Sheng-Yu Peng , Rodney Chandler , Pawan Tiwari , Rahul Bhatia , Eric Fogleman
CPC classification number: H04L7/0334 , H03M1/1215 , H03M1/1245
Abstract: A radio frequency (RF) receiver may comprise a first sampling module that is operable to sample in a first level at a particular main sampling rate; a plurality of second-level sampling modules, wherein each of the plurality of second-level sampling modules is operable to sample in a second level, an output of the first level, at a second sampling rate that is reduced compared to the main sampling rate; and a plurality of third-level modules, each comprising a plurality of third-stage sampling sub-modules that are operable to sample at a third sampling rate that is reduced compared to the second sampling rate, and a plurality of corresponding analog-to-digital conversion (ADC) sub-modules.
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公开(公告)号：US09559835B2
公开(公告)日：2017-01-31
申请号：US14563476
申请日：2014-12-08
Applicant: MaxLinear, Inc.
Inventor： Jianyu Zhu , Sheng-Yu Peng , Rodney Chandler , Pawan Tiwari , Rahul Bhatia , Eric Fogleman
CPC classification number: H04L7/0334 , H03M1/1215 , H03M1/1245
Abstract: A signal receiver may comprise circuitry for applying multi-level sampling to an input signal, using a plurality of sampling rates that comprises at least two different sampling rates, and circuitry for processing one or more outputs of the multi-level sampling. The processing may comprises sampling at a sampling rate that is different than each of the plurality of sampling rates used during the multi-level sampling and applying analog-to-digital conversion. At least one of the sampling rates used during the multi-level sampling and/or the sampling rate used during the processing may be set based on configuring of one or more clock signals used during the multi-level sampling and/or during the processing. At least one of the one or more clock signals may be configured based on reduction of frequency of a corresponding base clock signal.
Abstract translation: 信号接收机可以包括用于使用包括至少两个不同采样速率的多个采样速率以及用于处理多电平采样的一个或多个输出的电路将多电平采样应用于输入信号的电路。 处理可以包括以与在多级采样期间使用的多个采样率中的每一个不同的采样率进行采样并且应用模数转换。 在处理期间使用的多级采样和/或采样率期间使用的采样率中的至少一个可以基于在多级采样期间和/或处理期间使用的一个或多个时钟信号的配置来设置。 可以基于对应的基本时钟信号的频率的降低来配置一个或多个时钟信号中的至少一个。
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