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    Jitter improvement in serializer-deserializer (SerDes) transmitters
    1.
    发明授权
    Jitter improvement in serializer-deserializer (SerDes) transmitters 有权

    公开(公告)号：US10355725B2

    公开(公告)日：2019-07-16

    申请号：US16025831

    申请日：2018-07-02

    Applicant: MaxLinear, Inc.

    Inventor： Amir Hadji-Abdolhamid ,  Sheng Ye

    IPC: H04L1/20 ,  H04B1/04 ,  H04B15/02 ,  H03K3/01 ,  H03M9/00 ,  H04B1/717 ,  H04L12/841 ,  H04L12/26

    Abstract: Systems and methods are provided for handling jitter improvement in transmitters. During processing of input data for serial transmission, it may be determined if jitter may occur, and when jitter occurs one or more adjustments may be determined, based on dummy data, to reduce jitter in an output corresponding to the input data. The one or more adjustments may then be applied during processing of the input data, to reduce jitter in a serial output corresponding to the input data. The dummy data may be generated based on the input data. The dummy data may be configured such that it may generate corresponding dummy current pulses which may be used in controlling supply variations during generation of the serial output. The use of the dummy data may be selectively turned on or off.

    Transceiver array
    4.
    发明授权
    Transceiver array 有权

    公开(公告)号：US10103822B2

    公开(公告)日：2018-10-16

    申请号：US15668883

    申请日：2017-08-04

    Applicant: Maxlinear, Inc.

    Inventor： Curtis Ling ,  Sheng Ye

    IPC: H04B17/00 ,  H04B7/08 ,  H04B7/06 ,  H04B17/12 ,  H01Q3/24 ,  H01Q3/26 ,  H04B10/43

    Abstract: Each of a plurality of modules comprises a respective one of a plurality of antenna elements, and each of a subset of the plurality of modules comprising a respective one of a plurality of transceivers, wherein the plurality of modules are interconnected via one or more communication links. The circuitry may be operable to receive a calibration signal via the plurality of antenna elements, determine, for each one of the antenna elements, a time and/or phase of arrival of the calibration signal, calculate, based on the time and/or phase of arrival of the calibration signal at each of the plurality of antenna elements, electrical distances between the plurality of antenna elements on the one or more communication links, and calculate beamforming coefficients for use with the plurality of antenna elements based on the electrical distances.

    Method and system for time interleaved analog-to-digital converter timing mismatch estimation and compensation
    5.
    发明授权
    Method and system for time interleaved analog-to-digital converter timing mismatch estimation and compensation 有权

    公开(公告)号：US10097193B2

    公开(公告)日：2018-10-09

    申请号：US15812365

    申请日：2017-11-14

    Applicant: Maxlinear, Inc.

    Inventor： Pawandeep Taluja ,  Mingrui Zhu ,  Xuefeng Chen ,  Anand Anandakumar ,  Sheng Ye ,  Timothy Gallagher

    IPC: H03M1/06 ,  H04W56/00 ,  H03M1/50 ,  H03M1/12 ,  H03M1/10

    Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal utilizing a decorrelation algorithm on frequencies within a desired frequency bandwidth. The decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.

    Method and system for time interleaved analog-to-digital converter timing mismatch estimation and compensation
    9.
    发明授权
    Method and system for time interleaved analog-to-digital converter timing mismatch estimation and compensation 有权
    时间交错模数转换器定时失配估计和补偿的方法和系统

    公开(公告)号：US09577655B2

    公开(公告)日：2017-02-21

    申请号：US14920699

    申请日：2015-10-22

    Applicant: Maxlinear, Inc.

    Inventor： Pawandeep Taluja ,  Mingrui Zhu ,  Xuefeng Chen ,  Anand Anandakumar ,  Sheng Ye ,  Timothy Leo Gallagher

    IPC: H03M1/06 ,  H03M1/50 ,  H03M1/10 ,  H03M1/12 ,  H04L7/00 ,  H04L25/08 ,  H04W56/00

    CPC classification number: H03M1/0612 ,  H03M1/1009 ,  H03M1/1038 ,  H03M1/1215 ,  H03M1/50 ,  H04L7/0087 ,  H04L25/08 ,  H04W56/00

    Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is aliased onto a desired signal by a timing offset in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal. A decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.

    Abstract translation: 用于时间交织的模数转换器定时失配校准和补偿的方法和系统可以包括在芯片上接收模拟信号，使用时间交织的模数转换器（ADC）将模拟信号转换成数字信号， 并且通过估计期望的数字输出信号和阻塞信号之间的复数耦合系数，将在时间交错ADC中的定时偏移上的混叠在期望信号上的阻塞信号减少。 解相关算法可以包括对称自适应去相关算法。 所接收的模拟信号可以由芯片上的校准音发生器产生。 混叠信号可以与来自乘法器的输出信号相加。 复数耦合系数可以利用求和信号上的去相关算法来确定。 乘法器可以被配置为利用所确定的复耦合系数来消除阻塞信号。

    Method And System For A Sampled Loop Filter In A Phase Locked Loop (PLL)
    10.
    发明申请
    Method And System For A Sampled Loop Filter In A Phase Locked Loop (PLL) 有权
    锁相环（PLL）中采样环路滤波器的方法和系统

    公开(公告)号：US20170047932A1

    公开(公告)日：2017-02-16

    申请号：US15236369

    申请日：2016-08-12

    Applicant: Maxlinear, Inc.

    Inventor： Sangeetha Gopalakrishnan ,  Sheng Ye ,  Vamsi Paidi

    IPC: H03L7/085 ,  H03L7/197

    CPC classification number: H03L7/085 ,  H03L7/093 ,  H03L7/099 ,  H03L7/1974 ,  H03L7/1976

    Abstract: Methods and systems for a sampled loop filter in a phase locked loop (PLL) may comprise a phase locked loop (PLL) comprising a phase frequency detector, a sampled loop filter comprising a plurality of capacitors and at least one switch, a plurality of voltage controlled oscillators (VCOs) coupled to said sampled loop filter, and a frequency divider. The PLL generates at least one clock signal, and the sampled loop filter samples an output signal from the phase frequency detector when an average of charge provided to a first of the plurality of capacitors in the sampled loop filter is zero. The frequency divider may be a fractional-N divider. A second switch in said sampled loop filter may have switching times that are non-overlapping with switching times of the at least one switch. Capacitors may be coupled to ground from each terminal of the second switch.

    Abstract translation: 锁相环（PLL）中采样环路滤波器的方法和系统可以包括锁相环（PLL），其包括相位频率检测器，包括多个电容器和至少一个开关的采样环路滤波器，多个电压 耦合到所述采样环路滤波器的受控振荡器（VCO）和分频器。 当提供给采样环路滤波器中的多个电容器中的第一电容器的电荷的平均值为零时，PLL产生至少一个时钟信号，并且采样的环路滤波器对来自相位频率检测器的输出信号进行采样。 分频器可以是分数N分频器。 所述采样环路滤波器中的第二开关可以具有与至少一个开关的开关时间不重叠的开关时间。 电容器可以从第二开关的每个端子耦合到地。

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