公开(公告)号：US10651806B2

公开(公告)日：2020-05-12

申请号：US16268002

申请日：2019-02-05

Applicant: Maxlinear, Inc.

Inventor： Abhishek Jajoo ,  Vamsi Paidi

IPC: H03F3/45 ,  H03F3/195 ,  H03F1/52

Abstract: Methods and systems for a pseudo-differential low-noise amplifier at Ku-band may comprise a low-noise amplifier (LNA) integrated on a semiconductor die, where the LNA includes first and second differential pair transistors with an embedded inductor tail integrated on the semiconductor die. The embedded inductor tail may include: a first inductor with a first terminal capacitively-coupled to a gate terminal of the first differential pair transistor and a second terminal of the first inductor coupled to second, third, and fourth inductors. The second inductor may be coupled to a source terminal of the first differential pair transistor, the fourth inductor may be coupled to a source terminal of the second differential pair transistor, and the third inductor may be capacitively-coupled to a gate terminal of the second differential pair transistor and also to ground. The second inductor may be embedded within the first inductor.

公开(公告)号：US20160352295A1

公开(公告)日：2016-12-01

申请号：US15232056

申请日：2016-08-09

Applicant: Maxlinear, Inc.

Inventor： Abhishek Jajoo ,  Vamsi Paidi

IPC: H03F3/45 ,  H03F3/195 ,  H03F1/52

CPC classification number: H03F3/45179 ,  H03F1/523 ,  H03F3/195 ,  H03F3/45188 ,  H03F2200/171 ,  H03F2200/222 ,  H03F2200/294 ,  H03F2200/336 ,  H03F2200/451 ,  H03F2203/45166 ,  H03F2203/45386 ,  H03F2203/45464

Abstract: Methods and systems for a pseudo-differential low-noise amplifier at Ku-band may comprise a low-noise amplifier (LNA) integrated on a semiconductor die, where the LNA comprises differential pair transistors with an embedded inductor tail integrated on the semiconductor die. The embedded inductor tail may comprise: a first inductor with a first terminal capacitively-coupled to a gate terminal of a first transistor of the differential pair transistors and a second terminal of the first inductor coupled to second, third, and fourth inductors. The second inductor may be coupled to a source terminal of the first transistor of the differential pair transistors, the fourth inductor may be coupled to a source terminal of the second transistor of the differential pair transistors, and the third inductor may be capacitively-coupled to a gate terminal of the second transistor of the differential pair transistors and also to ground. The second inductor may be embedded within the first inductor.

Abstract translation: 用于Ku波段的伪差分低噪声放大器的方法和系统可以包括集成在半导体管芯上的低噪声放大器（LNA），其中LNA包括集成在半导体管芯上的嵌入式电感尾部的差分对晶体管。 嵌入式电感器尾部可以包括：第一电感器，其具有电容耦合到差分对晶体管的第一晶体管的栅极端子的第一端子和耦合到第二，第三和第四电感器的第一电感器的第二端子。 第二电感器可以耦合到差分对晶体管的第一晶体管的源极端子，第四电感器可以耦合到差分对晶体管的第二晶体管的源极端子，并且第三电感器可以电容耦合到 差分对晶体管的第二晶体管的栅极端子以及接地。 第二电感器可以嵌入在第一电感器内。

公开(公告)号：US20180091104A1

公开(公告)日：2018-03-29

申请号：US15805385

申请日：2017-11-07

Applicant: Maxlinear, Inc.

Inventor： Abhishek Jajoo ,  Vamsi Paidi

IPC: H03F3/45 ,  H03F3/195 ,  H03F1/52

CPC classification number: H03F3/45179 ,  H03F1/523 ,  H03F3/195 ,  H03F3/45188 ,  H03F2200/171 ,  H03F2200/222 ,  H03F2200/294 ,  H03F2200/336 ,  H03F2200/451 ,  H03F2203/45166 ,  H03F2203/45386 ,  H03F2203/45464

Abstract: Methods and systems for a pseudo-differential low-noise amplifier at Ku-band may comprise a low-noise amplifier (LNA) integrated on a semiconductor die, where the LNA includes first and second differential pair transistors with an embedded inductor tail integrated on the semiconductor die. The embedded inductor tail may include: a first inductor with a first terminal capacitively-coupled to a gate terminal of the first differential pair transistor and a second terminal of the first inductor coupled to second, third, and fourth inductors. The second inductor may be coupled to a source terminal of the first differential pair transistor, the fourth inductor may be coupled to a source terminal of the second differential pair transistor, and the third inductor may be capacitively-coupled to a gate terminal of the second differential pair transistor and also to ground. The second inductor may be embedded within the first inductor.

公开(公告)号：US09819319B2

公开(公告)日：2017-11-14

申请号：US15232056

申请日：2016-08-09

Applicant: Maxlinear, Inc.

Inventor： Abhishek Jajoo ,  Vamsi Paidi

IPC: H03F3/45 ,  H03F3/195 ,  H03F1/52

CPC classification number: H03F3/45179 ,  H03F1/523 ,  H03F3/195 ,  H03F3/45188 ,  H03F2200/171 ,  H03F2200/222 ,  H03F2200/294 ,  H03F2200/336 ,  H03F2200/451 ,  H03F2203/45166 ,  H03F2203/45386 ,  H03F2203/45464

Abstract: Methods and systems for a pseudo-differential low-noise amplifier at Ku-band may comprise a low-noise amplifier (LNA) integrated on a semiconductor die, where the LNA comprises differential pair transistors with an embedded inductor tail integrated on the semiconductor die. The embedded inductor tail may comprise: a first inductor with a first terminal capacitively-coupled to a gate terminal of a first transistor of the differential pair transistors and a second terminal of the first inductor coupled to second, third, and fourth inductors. The second inductor may be coupled to a source terminal of the first transistor of the differential pair transistors, the fourth inductor may be coupled to a source terminal of the second transistor of the differential pair transistors, and the third inductor may be capacitively-coupled to a gate terminal of the second transistor of the differential pair transistors and also to ground. The second inductor may be embedded within the first inductor.

公开(公告)号：US20190173441A1

公开(公告)日：2019-06-06

申请号：US16268002

申请日：2019-02-05

Applicant: Maxlinear, Inc.

Inventor： Abhishek Jajoo ,  Vamsi Paidi

IPC: H03F3/45 ,  H03F1/52 ,  H03F3/195

Abstract: Methods and systems for a pseudo-differential low-noise amplifier at Ku-band may comprise a low-noise amplifier (LNA) integrated on a semiconductor die, where the LNA includes first and second differential pair transistors with an embedded inductor tail integrated on the semiconductor die. The embedded inductor tail may include: a first inductor with a first terminal capacitively-coupled to a gate terminal of the first differential pair transistor and a second terminal of the first inductor coupled to second, third, and fourth inductors. The second inductor may be coupled to a source terminal of the first differential pair transistor, the fourth inductor may be coupled to a source terminal of the second differential pair transistor, and the third inductor may be capacitively-coupled to a gate terminal of the second differential pair transistor and also to ground. The second inductor may be embedded within the first inductor.

公开(公告)号：US09762181B2

公开(公告)日：2017-09-12

申请号：US15224530

申请日：2016-07-30

Applicant: Maxlinear, Inc.

Inventor： Abhishek Jajoo ,  Pawan Tiwari ,  Vamsi Paidi

IPC: H03K3/03 ,  H03B5/20 ,  H03L7/23 ,  H03B27/00

CPC classification number: H03B5/20 ,  H03B27/00 ,  H03B2200/009 ,  H03L7/23

Abstract: Methods and systems for a multi-core multi-mode voltage-controlled-oscillator (VCO) may comprise generating a plurality of oscillating signals utilizing a plurality of voltage controlled oscillators (VCOs) arranged symmetrically on an integrated circuit, where interconnects for the VCOs may be arranged in quiet zones at locations equidistant from each pair of the plurality of VCOs. An interconnection ring may be centered within the arranged VCOs that comprises at least two conductive lines that couple to output terminals of each of said plurality of VCOs. The plurality of VCOs may receive control signals from interconnects coupled to at least one conductive line in the interconnection ring. The plurality of VCOs may receive control signals from a conductive line in said interconnection ring. A positive terminal of a first VCO of a pair of adjacent VCOs of the plurality of VCOs may be coupled to a same conductive line of the interconnection ring as a negative terminal of a second of the pair of adjacent VCOs. The interconnection ring ay be circular. Impedances may couple the VCOs to the interconnection ring. Bias signals may be communicated to each of the plurality of VCOs from the interconnection ring. The plurality of VCOs may include four VCOs arranged equidistant from a center point.

公开(公告)号：US09419569B2

公开(公告)日：2016-08-16

申请号：US14260214

申请日：2014-04-23

Applicant: Maxlinear, Inc.

Inventor： Abhishek Jajoo ,  Vamsi Paidi

IPC: H03F3/45 ,  H03F3/195

CPC classification number: H03F3/45179 ,  H03F1/523 ,  H03F3/195 ,  H03F3/45188 ,  H03F2200/171 ,  H03F2200/222 ,  H03F2200/294 ,  H03F2200/336 ,  H03F2200/451 ,  H03F2203/45166 ,  H03F2203/45386 ,  H03F2203/45464

Abstract: Methods and systems for a pseudo-differential low-noise amplifier at Ku-band may comprise a low-noise amplifier (LNA) integrated on a semiconductor die, where the LNA comprises differential pair transistors with an embedded inductor tail integrated on the semiconductor die. The embedded inductor tail may comprise: a first inductor with a first terminal capacitively-coupled to a gate terminal of a first transistor of the differential pair transistors and a second terminal of the first inductor coupled to second, third, and fourth inductors. The second inductor may be coupled to a source terminal of the first transistor of the differential pair transistors, the fourth inductor may be coupled to a source terminal of the second transistor of the differential pair transistors, and the third inductor may be capacitively-coupled to a gate terminal of the second transistor of the differential pair transistors and also to ground. The second inductor may be embedded within the first inductor.

Abstract translation: 用于Ku波段的伪差分低噪声放大器的方法和系统可以包括集成在半导体管芯上的低噪声放大器（LNA），其中LNA包括集成在半导体管芯上的嵌入式电感尾部的差分对晶体管。 嵌入式电感器尾部可以包括：第一电感器，其具有电容耦合到差分对晶体管的第一晶体管的栅极端子的第一端子和耦合到第二，第三和第四电感器的第一电感器的第二端子。 第二电感器可以耦合到差分对晶体管的第一晶体管的源极端子，第四电感器可以耦合到差分对晶体管的第二晶体管的源极端子，并且第三电感器可以电容耦合到 差分对晶体管的第二晶体管的栅极端子以及接地。 第二电感器可以嵌入在第一电感器内。

公开(公告)号：US20140320206A1

公开(公告)日：2014-10-30

申请号：US14260214

申请日：2014-04-23

Applicant: Maxlinear, Inc.

Inventor： Abhishek Jajoo ,  Vamsi Paidi

IPC: H03F3/45

CPC classification number: H03F3/45179 ,  H03F1/523 ,  H03F3/195 ,  H03F3/45188 ,  H03F2200/171 ,  H03F2200/222 ,  H03F2200/294 ,  H03F2200/336 ,  H03F2200/451 ,  H03F2203/45166 ,  H03F2203/45386 ,  H03F2203/45464

Abstract: Methods and systems for a pseudo-differential low-noise amplifier at Ku-band may comprise a low-noise amplifier (LNA) integrated on a semiconductor die, where the LNA comprises differential pair transistors with an embedded inductor tail integrated on the semiconductor die. The embedded inductor tail may comprise: a first inductor with a first terminal capacitively-coupled to a gate terminal of a first transistor of the differential pair transistors and a second terminal of the first inductor coupled to second, third, and fourth inductors. The second inductor may be coupled to a source terminal of the first transistor of the differential pair transistors, the fourth inductor may be coupled to a source terminal of the second transistor of the differential pair transistors, and the third inductor may be capacitively-coupled to a gate terminal of the second transistor of the differential pair transistors and also to ground. The second inductor may be embedded within the first inductor.

Abstract translation: 用于Ku波段的伪差分低噪声放大器的方法和系统可以包括集成在半导体管芯上的低噪声放大器（LNA），其中LNA包括集成在半导体管芯上的嵌入式电感尾部的差分对晶体管。 嵌入式电感器尾部可以包括：第一电感器，其具有电容耦合到差分对晶体管的第一晶体管的栅极端子的第一端子和耦合到第二，第三和第四电感器的第一电感器的第二端子。 第二电感器可以耦合到差分对晶体管的第一晶体管的源极端子，第四电感器可以耦合到差分对晶体管的第二晶体管的源极端子，并且第三电感器可以电容耦合到 差分对晶体管的第二晶体管的栅极端子以及接地。 第二电感器可以嵌入在第一电感器内。

公开(公告)号：US10199998B2

公开(公告)日：2019-02-05

申请号：US15805385

申请日：2017-11-07

Applicant: Maxlinear, Inc.

Inventor： Abhishek Jajoo ,  Vamsi Paidi

IPC: H03F3/45 ,  H03F3/195 ,  H03F1/52

Abstract: Methods and systems for a pseudo-differential low-noise amplifier at Ku-band may comprise a low-noise amplifier (LNA) integrated on a semiconductor die, where the LNA includes first and second differential pair transistors with an embedded inductor tail integrated on the semiconductor die. The embedded inductor tail may include: a first inductor with a first terminal capacitively-coupled to a gate terminal of the first differential pair transistor and a second terminal of the first inductor coupled to second, third, and fourth inductors. The second inductor may be coupled to a source terminal of the first differential pair transistor, the fourth inductor may be coupled to a source terminal of the second differential pair transistor, and the third inductor may be capacitively-coupled to a gate terminal of the second differential pair transistor and also to ground. The second inductor may be embedded within the first inductor.

公开(公告)号：US20170373639A1

公开(公告)日：2017-12-28

申请号：US15699074

申请日：2017-09-08

Applicant: Maxlinear, Inc.

Inventor： Abhishek Jajoo ,  Pawan Tiwari ,  Vamsi Paidi

IPC: H03B5/20 ,  H03B27/00 ,  H03L7/23

CPC classification number: H03B5/20 ,  H03B27/00 ,  H03B2200/009 ,  H03L7/23

Abstract: Methods and systems for a multi-core multi-mode voltage-controlled-oscillator (VCO) may comprise generating a plurality of oscillating signals utilizing a plurality of voltage controlled oscillators (VCOs) arranged symmetrically on an integrated circuit, where interconnects for the VCOs may be arranged in quiet zones at locations equidistant from each pair of VCOs. An interconnection ring may be centered within the arranged VCOs that comprises at least two conductive lines that couple to output terminals each VCO. The VCOs may receive control signals from interconnects coupled to at least one conductive line in the interconnection ring. The VCOs may receive control signals from a conductive line in said interconnection ring. A positive terminal of a first VCO of a pair of adjacent VCOs of the plurality of VCOs may be coupled to a same conductive line of the interconnection ring as a negative terminal of a second of the pair of adjacent VCOs.