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    LOW-POWER BLOCK CODE FORWARD ERROR CORRECTION DECODER
    1.
    发明申请
    LOW-POWER BLOCK CODE FORWARD ERROR CORRECTION DECODER 审中-公开

    公开(公告)号：US20190305800A1

    公开(公告)日：2019-10-03

    申请号：US16367538

    申请日：2019-03-28

    Applicant: Maxlinear, Inc.

    Inventor： Youzhe Fan ,  Jining Duan

    IPC: H03M13/15 ,  H03M13/11 ,  H03M13/00

    Abstract: A system comprises a forward error correction decoder comprising syndrome computation circuitry, key-equation solver circuitry, and search and evaluator circuitry. The syndrome computation circuitry may comprise a plurality of syndrome compute units connected in parallel. The syndrome computation circuitry may be dynamically configurable to vary a quantity of the syndrome compute units used for processing of a codeword based on conditions of a channel over which the codeword was received. The syndrome computation circuitry may be operable to use a first quantity of the syndrome compute units for processing of a first codeword received over the channel when the channel is characterized by a first bit error rate and a second quantity of the syndrome compute units for processing of a second codeword received over the channel when the channel is characterized by a second bit error rate.

    LOW-POWER BLOCK CODE FORWARD ERROR CORRECTION DECODER
    6.
    发明公开
    LOW-POWER BLOCK CODE FORWARD ERROR CORRECTION DECODER 审中-公开

    公开(公告)号：US20230412196A1

    公开(公告)日：2023-12-21

    申请号：US18461361

    申请日：2023-09-05

    Applicant: Maxlinear, Inc.

    Inventor： Youzhe Fan ,  Jining Duan

    IPC: H03M13/15 ,  H03M13/00 ,  H03M13/11

    CPC classification number: H03M13/1545 ,  H03M13/6561 ,  H03M13/157 ,  H03M13/1105

    Abstract: A system comprises a forward error correction decoder comprising syndrome computation circuitry, key-equation solver circuitry, and search and evaluator circuitry. The syndrome computation circuitry may comprise a plurality of syndrome compute units connected in parallel. The syndrome computation circuitry may be dynamically configurable to vary a quantity of the syndrome compute units used for processing of a codeword based on conditions of a channel over which the codeword was received. The syndrome computation circuitry may be operable to use a first quantity of the syndrome compute units for processing of a first codeword received over the channel when the channel is characterized by a first bit error rate and a second quantity of the syndrome compute units for processing of a second codeword received over the channel when the channel is characterized by a second bit error rate.

    Low-power block code forward error correction decoder
    8.
    发明授权
    Low-power block code forward error correction decoder 有权

    公开(公告)号：US11750223B2

    公开(公告)日：2023-09-05

    申请号：US16367538

    申请日：2019-03-28

    Applicant: Maxlinear, Inc.

    Inventor： Youzhe Fan ,  Jining Duan

    IPC: H03M13/15 ,  H03M13/00 ,  H03M13/11

    CPC classification number: H03M13/1545 ,  H03M13/1105 ,  H03M13/157 ,  H03M13/6561

    Abstract: A system comprises a forward error correction decoder comprising syndrome computation circuitry, key-equation solver circuitry, and search and evaluator circuitry. The syndrome computation circuitry may comprise a plurality of syndrome compute units connected in parallel. The syndrome computation circuitry may be dynamically configurable to vary a quantity of the syndrome compute units used for processing of a codeword based on conditions of a channel over which the codeword was received. The syndrome computation circuitry may be operable to use a first quantity of the syndrome compute units for processing of a first codeword received over the channel when the channel is characterized by a first bit error rate and a second quantity of the syndrome compute units for processing of a second codeword received over the channel when the channel is characterized by a second bit error rate.

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