公开(公告)号：US09154154B2

公开(公告)日：2015-10-06

申请号：US14471587

申请日：2014-08-28

Applicant: Maxlinear, Inc.

Inventor： Rajesh Zele ,  Gaurav Chandra

IPC: H03M1/66 ,  H03M1/70

CPC classification number: H03M1/66 ,  H03F3/45192 ,  H03F2203/45526 ,  H03M1/70 ,  H03M1/742

Abstract: Methods and systems for a low input voltage low impedance termination stage for current inputs may include, in a semiconductor die, generating an output current proportional to an input signal, where the output current is generated by an output stage that may include a pair of input cascode transistors and at least one pair of stacked output transistors. A source-follower feedback path for the input cascode transistors may include a feedback transistor with its gate terminal coupled to a drain terminal of a first of the input cascode transistors, a drain of the feedback transistor coupled to a supply voltage, and a source terminal of the feedback transistor coupled to a current source that is coupled to ground. A current source may be coupled to the drain of the first of the input cascode transistors. The supply voltage may be coupled to the stacked output transistors via a load resistor.

Abstract translation: 用于电流输入的低输入电压低阻抗终端级的方法和系统可以包括在半导体管芯中产生与输入信号成比例的输出电流，其中输出电流由输出级产生，输出级可包括一对输入 共源共栅晶体管和至少一对堆叠输出晶体管。 用于输入共源共栅晶体管的源极 - 跟随器反馈路径可以包括其栅极端子耦合到输入共源共栅晶体管中的第一个的漏极端子的反馈晶体管，耦合到电源电压的反馈晶体管的漏极和源极端子 耦合到耦合到地的电流源的反馈晶体管。 电流源可以耦合到第一输入共源共栅晶体管的漏极。 电源电压可以经由负载电阻器耦合到堆叠的输出晶体管。

公开(公告)号：US09397686B2

公开(公告)日：2016-07-19

申请号：US14865582

申请日：2015-09-25

Applicant: Maxlinear, Inc.

Inventor： Rajesh Zele ,  Gaurav Chandra

IPC: H03M1/66 ,  H03M1/70 ,  H03F3/45 ,  H03M1/74

CPC classification number: H03M1/66 ,  H03F3/45192 ,  H03F2203/45526 ,  H03M1/70 ,  H03M1/742

Abstract: A low input voltage low impedance termination stage for current inputs may include an output stage for an electrical circuit, the output stage including input cascode transistors and stacked output transistors. A source-follower feedback path for the input cascode transistors may include a feedback transistor with its gate terminal coupled to a drain terminal of a first of the input cascode transistors, a drain of the feedback transistor coupled to a supply voltage, and a source terminal of the feedback transistor coupled to a current source. A current source may be coupled to the drain of the first of the input cascode transistors. The supply voltage may be coupled to the stacked output transistors via a load resistor. The input cascode transistors, the feedback transistor, and the stacked output transistors may include complementary metal-oxide semiconductor (CMOS) transistors.

Abstract translation: 用于电流输入的低输入电压低阻抗终端级可以包括用于电路的输出级，输出级包括输入共源共栅晶体管和堆叠输出晶体管。 用于输入共源共栅晶体管的源极 - 跟随器反馈路径可以包括其栅极端子耦合到输入共源共栅晶体管中的第一个的漏极端子的反馈晶体管，耦合到电源电压的反馈晶体管的漏极和源极端子 耦合到电流源的反馈晶体管。 电流源可以耦合到第一输入共源共栅晶体管的漏极。 电源电压可以经由负载电阻器耦合到堆叠的输出晶体管。 输入共源共栅晶体管，反馈晶体管和堆叠输出晶体管可以包括互补金属氧化物半导体（CMOS）晶体管。

公开(公告)号：US20160020780A1

公开(公告)日：2016-01-21

申请号：US14865582

申请日：2015-09-25

Applicant: Maxlinear, Inc.

Inventor： Rajesh Zele ,  Gaurav Chandra

IPC: H03M1/66

CPC classification number: H03M1/66 ,  H03F3/45192 ,  H03F2203/45526 ,  H03M1/70 ,  H03M1/742

Abstract: A low input voltage low impedance termination stage for current inputs is disclosed and may include an output stage for an electrical circuit, the output stage including input cascode transistors and stacked output transistors, wherein a source-follower feedback path for the input cascode transistors may include a feedback transistor with its gate terminal coupled to a drain terminal of a first of the input cascode transistors, a drain of the feedback transistor coupled to a supply voltage, and a source terminal of the feedback transistor coupled to a current source. A current source may be coupled to the drain of the first of the input cascode transistors. The supply voltage may be coupled to the stacked output transistors via a load resistor. The input cascode transistors, the feedback transistor, and the stacked output transistors may include complementary metal-oxide semiconductor (CMOS) transistors.

Abstract translation: 公开了用于电流输入的低输入电压低阻抗终端级，并且可以包括用于电路的输出级，输出级包括输入共源共栅晶体管和堆叠输出晶体管，其中用于输入共源共栅晶体管的源极 - 跟随器反馈路径可以包括 反馈晶体管，其栅极端子耦合到输入共源共栅晶体管中的第一个的漏极端子，耦合到电源电压的反馈晶体管的漏极和耦合到电流源的反馈晶体管的源极端子。 电流源可以耦合到第一输入共源共栅晶体管的漏极。 电源电压可以经由负载电阻器耦合到堆叠的输出晶体管。 输入共源共栅晶体管，反馈晶体管和堆叠输出晶体管可以包括互补金属氧化物半导体（CMOS）晶体管。

公开(公告)号：US20150061910A1

公开(公告)日：2015-03-05

申请号：US14471587

申请日：2014-08-28

Applicant: Maxlinear, Inc.

Inventor： Rajesh Zele ,  Gaurav Chandra

IPC: H03M1/70

CPC classification number: H03M1/66 ,  H03F3/45192 ,  H03F2203/45526 ,  H03M1/70 ,  H03M1/742

Abstract: Methods and systems for a low input voltage low impedance termination stage for current inputs may comprise, in a semiconductor die, generating an output current proportional to an input signal, where the output current is generated by an output stage that may include a pair of input cascode transistors and at least one pair of stacked output transistors. A source-follower feedback path for the input cascode transistors may include a feedback transistor with its gate terminal coupled to a drain terminal of a first of the input cascode transistors, a drain of the feedback transistor coupled to a supply voltage, and a source terminal of the feedback transistor coupled to a current source that is coupled to ground. A current source may be coupled to the drain of the first of the input cascode transistors. The supply voltage may be coupled to the stacked output transistors via a load resistor.

Abstract translation: 用于电流输入的用于低输入电压低阻抗终止级的方法和系统可包括在半导体管芯中产生与输入信号成比例的输出电流，其中输出电流由输出级产生，输出级可包括一对输入 共源共栅晶体管和至少一对堆叠输出晶体管。 用于输入共源共栅晶体管的源极跟随器反馈路径可以包括反馈晶体管，其栅极端子耦合到输入共源共栅晶体管中的第一个的漏极端子，耦合到电源电压的反馈晶体管的漏极和源极端子 耦合到耦合到地的电流源的反馈晶体管。 电流源可以耦合到第一输入共源共栅晶体管的漏极。 电源电压可以经由负载电阻器耦合到堆叠的输出晶体管。