公开(公告)号：US10404260B2

公开(公告)日：2019-09-03

申请号：US15906578

申请日：2018-02-27

Applicant: Maxlinear, Inc.

Inventor： Sangeetha Gopalakrishnan ,  Sheng Ye ,  Vamsi Paidi ,  Raghava Manas Bachu

IPC: H03L7/00 ,  H03L7/085 ,  H03L7/197 ,  H03L7/093 ,  H03L7/099

Abstract: Methods and systems for a sampled loop filter in a phase locked loop (PLL) may comprise a phase locked loop (PLL) comprising a phase frequency detector, a sampled loop filter comprising a plurality of capacitors and at least one switch, a plurality of voltage controlled oscillators (VCOs) coupled to said sampled loop filter, and a frequency divider. The PLL generates at least one clock signal, and the sampled loop filter samples an output signal from the phase frequency detector when an average of charge provided to a first of the plurality of capacitors in the sampled loop filter is zero. The frequency divider may be a fractional-N divider. A second switch in said sampled loop filter may have switching times that are non-overlapping with switching times of the at least one switch. Capacitors may be coupled to ground from each terminal of the second switch.

公开(公告)号：US09923547B2

公开(公告)日：2018-03-20

申请号：US15236372

申请日：2016-08-12

Applicant: Maxlinear, Inc.

Inventor： Wenjian Chen ,  Sangeetha Gopalakrishnan ,  Raghava Manas Bachu ,  Vamsi Paidi

IPC: H03B5/12 ,  H03H11/30 ,  H03B1/00 ,  H03B27/00 ,  H03B5/00 ,  H03B25/00

CPC classification number: H03H11/30 ,  H03B1/00 ,  H03B5/00 ,  H03B5/1237 ,  H03B25/00 ,  H03B27/00 ,  H03B2200/0072

Abstract: Methods and systems for a distributed transmission line multiplexer for a multi-core multi-mode voltage-controlled oscillator (VCO) may comprise a plurality of voltage controlled oscillators (VCOs) arranged adjacent to each other, where each of the plurality of VCOs are operable to generate an output signal at a configurable frequency, an impedance matching circuit comprising a respective driver and impedance matching elements coupled to each of the plurality of VCOs, and an output device coupled to the impedance matching circuit. The impedance matching elements may include capacitors and inductors. Between each adjacent pair of the respective drivers coupled to each of the plurality of VCOs, the impedance matching elements may include two inductors coupled in series between the drivers and a capacitor coupled to ground and to a common node between the two inductors. Impedance values of the capacitors and inductors may be configurable. The impedance matching elements may include a resistor coupled to a bias voltage VDD and to a common node with a capacitor that is coupled to ground, where the common node is coupled to one of the inductors. The output device may include a prescaler that is an integer or fractional frequency-N divider, or a buffer. The respective drivers coupled to each of the plurality of VCOs may be configured to provide a constant output power no matter which of said plurality of VCOs is enabled.

公开(公告)号：US20170047932A1

公开(公告)日：2017-02-16

申请号：US15236369

申请日：2016-08-12

Applicant: Maxlinear, Inc.

Inventor： Sangeetha Gopalakrishnan ,  Sheng Ye ,  Vamsi Paidi

IPC: H03L7/085 ,  H03L7/197

CPC classification number: H03L7/085 ,  H03L7/093 ,  H03L7/099 ,  H03L7/1974 ,  H03L7/1976

Abstract: Methods and systems for a sampled loop filter in a phase locked loop (PLL) may comprise a phase locked loop (PLL) comprising a phase frequency detector, a sampled loop filter comprising a plurality of capacitors and at least one switch, a plurality of voltage controlled oscillators (VCOs) coupled to said sampled loop filter, and a frequency divider. The PLL generates at least one clock signal, and the sampled loop filter samples an output signal from the phase frequency detector when an average of charge provided to a first of the plurality of capacitors in the sampled loop filter is zero. The frequency divider may be a fractional-N divider. A second switch in said sampled loop filter may have switching times that are non-overlapping with switching times of the at least one switch. Capacitors may be coupled to ground from each terminal of the second switch.

Abstract translation: 锁相环（PLL）中采样环路滤波器的方法和系统可以包括锁相环（PLL），其包括相位频率检测器，包括多个电容器和至少一个开关的采样环路滤波器，多个电压 耦合到所述采样环路滤波器的受控振荡器（VCO）和分频器。 当提供给采样环路滤波器中的多个电容器中的第一电容器的电荷的平均值为零时，PLL产生至少一个时钟信号，并且采样的环路滤波器对来自相位频率检测器的输出信号进行采样。 分频器可以是分数N分频器。 所述采样环路滤波器中的第二开关可以具有与至少一个开关的开关时间不重叠的开关时间。 电容器可以从第二开关的每个端子耦合到地。

公开(公告)号：US10523191B2

公开(公告)日：2019-12-31

申请号：US15651290

申请日：2017-07-17

Applicant: Maxlinear, Inc.

Inventor： Sangeetha Gopalakrishnan ,  Wenjian Chen ,  Vamsi Paidi

IPC: H03K17/00 ,  H03B5/02 ,  H03H11/02 ,  H03H11/34

Abstract: Aspects of methods and systems for high frequency signal selection are provided. The system for high frequency signal selection comprises a first driver and a second driver. The first driver is able to receive a first high frequency input, and the second driver is able to receive a second high frequency input. The output of the first driver is operably coupled, via a first inductive element, to a first resistive load and a first buffer, and the second driver is operably coupled, via a second inductive element, to the output of the first driver. One or both of the first high frequency input and the second high frequency input may be transferred to the first buffer by selectively enabling a current to one or both of the first driver and the second driver, respectively.

公开(公告)号：US20190280648A1

公开(公告)日：2019-09-12

申请号：US15913127

申请日：2018-03-06

Applicant: Maxlinear, Inc.

Inventor： Wenjian Chen ,  Sangeetha Gopalakrishnan ,  Raghava Manas Bachu ,  Vamsi Paidi

IPC: H03B5/12 ,  H03L7/24 ,  H03L5/02 ,  H03H7/40

Abstract: Methods and systems for a distributed transmission line multiplexer for a multi-core multi-mode voltage-controlled oscillator (VCO) may comprise a plurality of voltage controlled oscillators (VCOs) arranged adjacent to each other, where each of the plurality of VCOs are operable to generate an output signal at a configurable frequency, an impedance matching circuit comprising a respective driver and impedance matching elements coupled to each of the plurality of VCOs, and an output device coupled to the impedance matching circuit. The impedance matching elements may include capacitors and inductors. Between each adjacent pair of the respective drivers coupled to each of the plurality of VCOs, the impedance matching elements may include two inductors coupled in series between the drivers and a capacitor coupled to ground and to a common node between the two inductors. Impedance values of the capacitors and inductors may be configurable.

公开(公告)号：US09906227B2

公开(公告)日：2018-02-27

申请号：US15236369

申请日：2016-08-12

Applicant: Maxlinear, Inc.

Inventor： Sangeetha Gopalakrishnan ,  Sheng Ye ,  Vamsi Paidi

IPC: H03L7/00 ,  H03L7/085 ,  H03L7/197 ,  H03L7/093 ,  H03L7/099

CPC classification number: H03L7/085 ,  H03L7/093 ,  H03L7/099 ,  H03L7/1974 ,  H03L7/1976

Abstract: Methods and systems for a sampled loop filter in a phase locked loop (PLL) may comprise a phase locked loop (PLL) comprising a phase frequency detector, a sampled loop filter comprising a plurality of capacitors and at least one switch, a plurality of voltage controlled oscillators (VCOs) coupled to said sampled loop filter, and a frequency divider. The PLL generates at least one clock signal, and the sampled loop filter samples an output signal from the phase frequency detector when an average of charge provided to a first of the plurality of capacitors in the sampled loop filter is zero. The frequency divider may be a fractional-N divider. A second switch in said sampled loop filter may have switching times that are non-overlapping with switching times of the at least one switch. Capacitors may be coupled to ground from each terminal of the second switch.

公开(公告)号：US20180019738A1

公开(公告)日：2018-01-18

申请号：US15651290

申请日：2017-07-17

Applicant: Maxlinear, Inc.

Inventor： Sangeetha Gopalakrishnan ,  Wenjian Chen ,  Vamsi Paidi

IPC: H03K17/00 ,  H03B5/02

Abstract: Aspects of methods and systems for high frequency signal selection are provided. The system for high frequency signal selection comprises a first driver and a second driver. The first driver is able to receive a first high frequency input, and the second driver is able to receive a second high frequency input. The output of the first driver is operably coupled, via a first inductive element, to a first resistive load and a first buffer, and the second driver is operably coupled, via a second inductive element, to the output of the first driver. One or both of the first high frequency input and the second high frequency input may be transferred to the first buffer by selectively enabling a current to one or both of the first driver and the second driver, respectively.

公开(公告)号：US20180191357A1

公开(公告)日：2018-07-05

申请号：US15906578

申请日：2018-02-27

Applicant: Maxlinear, Inc.

Inventor： Sangeetha Gopalakrishnan ,  Sheng Ye ,  Vamsi Paidi ,  Raghava Manas Bachu

IPC: H03L7/085 ,  H03L7/099 ,  H03L7/197 ,  H03L7/093

CPC classification number: H03L7/085 ,  H03L7/093 ,  H03L7/099 ,  H03L7/1974 ,  H03L7/1976

Abstract: Methods and systems for a sampled loop filter in a phase locked loop (PLL) may comprise a phase locked loop (PLL) comprising a phase frequency detector, a sampled loop filter comprising a plurality of capacitors and at least one switch, a plurality of voltage controlled oscillators (VCOs) coupled to said sampled loop filter, and a frequency divider. The PLL generates at least one clock signal, and the sampled loop filter samples an output signal from the phase frequency detector when an average of charge provided to a first of the plurality of capacitors in the sampled loop filter is zero. The frequency divider may be a fractional-N divider. A second switch in said sampled loop filter may have switching times that are non-overlapping with switching times of the at least one switch. Capacitors may be coupled to ground from each terminal of the second switch.

公开(公告)号：US20170047891A1

公开(公告)日：2017-02-16

申请号：US15236372

申请日：2016-08-12

Applicant: Maxlinear, Inc.

Inventor： Wenjian Chen ,  Sangeetha Gopalakrishnan ,  Raghava Manas Bachu ,  Vamsi Paidi

IPC: H03B5/12 ,  H03H11/30 ,  H03L7/197

CPC classification number: H03H11/30 ,  H03B1/00 ,  H03B5/00 ,  H03B5/1237 ,  H03B25/00 ,  H03B27/00 ,  H03B2200/0072

Abstract: Methods and systems for a distributed transmission line multiplexer for a multi-core multi-mode voltage-controlled oscillator (VCO) may comprise a plurality of voltage controlled oscillators (VCOs) arranged adjacent to each other, where each of the plurality of VCOs are operable to generate an output signal at a configurable frequency, an impedance matching circuit comprising a respective driver and impedance matching elements coupled to each of the plurality of VCOs, and an output device coupled to the impedance matching circuit. The impedance matching elements may include capacitors and inductors. Between each adjacent pair of the respective drivers coupled to each of the plurality of VCOs, the impedance matching elements may include two inductors coupled in series between the drivers and a capacitor coupled to ground and to a common node between the two inductors. Impedance values of the capacitors and inductors may be configurable. The impedance matching elements may include a resistor coupled to a bias voltage VDD and to a common node with a capacitor that is coupled to ground, where the common node is coupled to one of the inductors. The output device may include a prescaler that is an integer or fractional frequency-N divider, or a buffer. The respective drivers coupled to each of the plurality of VCOs may be configured to provide a constant output power no matter which of said plurality of VCOs is enabled.

Abstract translation: 用于多核多模式压控振荡器（VCO）的分布式传输线路多路复用器的方法和系统可以包括彼此相邻布置的多个压控振荡器（VCO），其中多个VCO中的每一个可操作 以可配置的频率产生输出信号，阻抗匹配电路包括耦合到所述多个VCO中的每一个的相应的驱动器和阻抗匹配元件，以及耦合到所述阻抗匹配电路的输出装置。 阻抗匹配元件可以包括电容器和电感器。 在耦合到多个VCO中的每一个的相应驱动器的每个相邻的驱动器对之间，阻抗匹配元件可以包括串联耦合在驱动器之间的两个电感器和耦合到地的电容器和两个电感器之间的公共节点。 电容器和电感器的阻抗值可以是可配置的。 阻抗匹配元件可以包括耦合到偏置电压VDD的电阻器和耦合到地的电容器的公共节点，其中公共节点耦合到电感器之一。 输出设备可以包括预分频器，其是整数或分数频率N分频器或缓冲器。 耦合到多个VCO中的每一个的相应驱动器可以被配置为提供恒定的输出功率，而不管所述多个VCO中的哪一个被使能。