-
公开(公告)号：US10326462B2
公开(公告)日：2019-06-18
申请号：US16154167
申请日：2018-10-08
Applicant: Maxlinear, Inc.
Inventor： Pawandeep Taluja , Mingrui Zhu , Xuefeng Chen , Anand Anandakumar , Sheng Ye , Timothy Gallagher
Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal utilizing a decorrelation algorithm on frequencies within a desired frequency bandwidth. The decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.
-
公开(公告)号：US10320330B2
公开(公告)日：2019-06-11
申请号：US15831572
申请日：2017-12-05
Applicant: MaxLinear, Inc.
Inventor： Xuefeng Chen , Hosein Zareie
Abstract: Systems and methods are provided for generating reference signals with high interference immunity. A signal source may generate reference signals having a particular reference frequency based on characteristics of the source of the reference signals, for use in driving at least one component in a system. One or more processing may then process the generated reference signals, based on particular frequency positions relative to the particular reference frequency and other operations and/or components of the system. The processing may include filtering at the particular frequency positions. The particular frequency positions may correspond to the harmonics positions of the particular reference frequency. The signal source may be a crystal oscillator.
-
公开(公告)号：US10050614B2
公开(公告)日：2018-08-14
申请号：US15793581
申请日：2017-10-25
Applicant: Maxlinear, Inc.
Inventor： Yongjian Tang , Xuefeng Chen
Abstract: Methods and systems for reliable bootstrapping switches may comprise sampling a received signal with a bootstrapping switch, where the bootstrapping switch comprises a switching metal-oxide semiconductor (MOS) transistor having a pull-down path coupled to a gate terminal of the switching MOS transistor, wherein: source terminals of both a diode-connected transistor and a second MOS transistor are coupled to the gate terminal of the switching MOS transistor; drain terminals of both the diode-connected transistor and the second MOS transistor are coupled to a source terminal of a third MOS transistor, the third MOS transistor coupled in series with a fourth MOS transistor; and a drain terminal of the fourth MOS transistor is coupled to ground. The third and fourth MOS transistors may be in series with the second MOS transistor. A gate terminal of the fourth transistor may be switched from ground to a supply voltage to activate the pull-down path.
-
公开(公告)号：US09825640B2
公开(公告)日：2017-11-21
申请号：US15436088
申请日：2017-02-17
Applicant: Maxlinear, Inc.
Inventor： Pawandeep Taluja , Mingrui Zhu , Xuefeng Chen , Anand Anandakumar , Sheng Ye , Timothy Leo Gallagher
CPC classification number: H03M1/0612 , H03M1/1009 , H03M1/1038 , H03M1/1215 , H03M1/50 , H04L7/0087 , H04L25/08 , H04W56/00
Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal utilizing a decorrelation algorithm on frequencies within a desired frequency bandwidth. The decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.
-
5.发明申请Method and system for Time Interleaved Analog-To-Digital Converter Timing Mismatch Estimation And Compensation 有权时间交错模数转换器时序不匹配估计和补偿的方法和系统公开(公告)号：US20160043731A1
公开(公告)日：2016-02-11
申请号：US14920699
申请日：2015-10-22
Applicant: Maxlinear, Inc.
Inventor： Pawandeep Taluja , Mingrui Zhu , Xuefeng Chen , Anand Anandakumer , Sheng Ye , Timothy Leo Gallagher
CPC classification number: H03M1/0612 , H03M1/1009 , H03M1/1038 , H03M1/1215 , H03M1/50 , H04L7/0087 , H04L25/08 , H04W56/00
Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may comprise receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is aliased onto a desired signal by a timing offset in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal. A decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.
Abstract translation: 用于时间交织的模数转换器定时失配校准和补偿的方法和系统可以包括在芯片上接收模拟信号，利用时间交织的模数转换器（ADC）将模拟信号转换成数字信号， 以及通过估计期望的数字输出信号和阻塞信号之间的复数耦合系数，将在时间交错ADC中的定时偏移上的混叠在期望信号上的阻塞信号减少。 解相关算法可以包括对称自适应去相关算法。 所接收的模拟信号可以由芯片上的校准音发生器产生。 混叠信号可以与来自乘法器的输出信号相加。 复数耦合系数可以利用求和信号上的去相关算法来确定。 乘法器可以被配置为利用所确定的复耦合系数来消除阻塞信号。
-
Patent Agency Ranking
6.发明授权Method and system for time interleaved analog-to-digital converter timing mismatch estimation and compensation 有权时间交错模数转换器定时失配估计和补偿的方法和系统公开(公告)号：US09172386B2
公开(公告)日：2015-10-27
申请号：US14590250
申请日：2015-01-06
Applicant: Maxlinear, Inc.
Inventor： Pawandeep Taluja , Mingrui Zhu , Xuefeng Chen , Anand Anandakumar , Sheng Ye , Timothy Leo Gallagher
CPC classification number: H03M1/0612 , H03M1/1009 , H03M1/1038 , H03M1/1215 , H03M1/50 , H04L7/0087 , H04L25/08 , H04W56/00
Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may comprise receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal. A decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.
Abstract translation: 用于时间交织的模数转换器定时失配校准和补偿的方法和系统可以包括在芯片上接收模拟信号，利用时间交织的模数转换器（ADC）将模拟信号转换成数字信号， 并且通过估计期望的数字输出信号和阻塞信号之间的复耦合系数来减少由时间交错ADC中的定时偏移产生的阻塞信号。 解相关算法可以包括对称自适应去相关算法。 所接收的模拟信号可以由芯片上的校准音发生器产生。 混叠信号可以与来自乘法器的输出信号相加。 复数耦合系数可以利用求和信号上的去相关算法来确定。 乘法器可以被配置为利用所确定的复耦合系数来消除阻塞信号。
-
7.发明授权Method and system for asynchronous successive approximation register (SAR) analog-to-digital converters (ADCs) 有权用于异步逐次逼近寄存器（SAR）模数转换器（ADC）的方法和系统公开(公告)号：US09136859B2
公开(公告)日：2015-09-15
申请号：US14585656
申请日：2014-12-30
Applicant: MaxLinear, Inc.
Inventor： Eric Fogleman , Sheng Ye , Xuefeng Chen , Kok Lim Chan
Abstract: An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.
Abstract translation: 在每个数模转换器（DAC）码字中利用一个或多个重叠冗余位的异步逐次逼近寄存器模数转换器（SAR ADC）可操作以产生指示每个数 - 模转换器 比较步骤，表示每个比较步骤的输出决定是有效的。 可以基于产生的指示信号来启动定时器。 可以产生超时信号，该超时信号抢占指示信号并强制先占决定，其中先占决定将一个或多个剩余的比特设置为相应的数模转换器中的一个或多个重叠的冗余比特，但不包括其中的一个或多个重叠的冗余比特 用于当前比较步骤的代码字到特定值。 例如，可以将一个或多个剩余比特设置为从在紧接的前一决定中确定的比特的值导出的值。
-
8.发明授权Method and system for asynchronous successive approximation register (SAR) analog-to-digital converters (ADCs) 有权用于异步逐次逼近寄存器（SAR）模数转换器（ADC）的方法和系统公开(公告)号：US08922415B2
公开(公告)日：2014-12-30
申请号：US13964043
申请日：2013-08-10
Applicant: MaxLinear, Inc.
Inventor： Eric Fogleman , Sheng Ye , Xuefeng Chen , Kok Lim Chan
Abstract: An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.
Abstract translation: 在每个数模转换器（DAC）码字中利用一个或多个重叠冗余位的异步逐次逼近寄存器模数转换器（SAR ADC）可操作以产生指示每个数 - 模转换器 比较步骤，表示每个比较步骤的输出决定是有效的。 可以基于产生的指示信号来启动定时器。 可以产生超时信号，该超时信号抢占指示信号并强制先占决定，其中抢占决定将一个或多个剩余的比特设置为相应的数模转换器中的一个或多个重叠的冗余比特，但不包括其中的一个或多个重叠的冗余比特 用于当前比较步骤的代码字到特定值。 例如，可以将一个或多个剩余比特设置为从在紧接的前一决定中确定的比特的值导出的值。
-
9.发明申请METHOD AND SYSTEM FOR ASYNCHRONOUS SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS (ADCS) 有权非线性随机逼近寄存器（SAR）模数转换器（ADCS）的方法与系统公开(公告)号：US20140043175A1
公开(公告)日：2014-02-13
申请号：US13964043
申请日：2013-08-10
Applicant: MaxLinear, Inc.
Inventor： Eric Fogleman , Sheng Ye , Xuefeng Chen , Kok Lim Chan
IPC: H03M1/46
Abstract: An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.
Abstract translation: 在每个数模转换器（DAC）码字中利用一个或多个重叠冗余位的异步逐次逼近寄存器模数转换器（SAR ADC）可操作以产生指示每个数 - 模转换器 比较步骤，表示每个比较步骤的输出决定是有效的。 可以基于产生的指示信号来启动定时器。 可以产生超时信号，该超时信号抢占指示信号并强制先占决定，其中抢占决定将一个或多个剩余的比特设置为相应的数模转换器中的一个或多个重叠的冗余比特，但不包括其中的一个或多个重叠的冗余比特 用于当前比较步骤的代码字到特定值。 例如，可以将一个或多个剩余比特设置为从在紧接的前一决定中确定的比特的值导出的值。
-
公开(公告)号：US10355686B2
公开(公告)日：2019-07-16
申请号：US16057499
申请日：2018-08-07
Applicant: Maxlinear, Inc.
Inventor： Yongjian Tang , Xuefeng Chen
IPC: H03K17/06 , H03K17/687
Abstract: Methods and systems for reliable bootstrapping switches may comprise sampling a received signal with a bootstrapping switch, where the bootstrapping switch comprises a switching metal-oxide semiconductor (MOS) transistor having a pull-down path coupled to a gate terminal of the switching MOS transistor, wherein: source terminals of both a diode-connected transistor and a second MOS transistor are coupled to the gate terminal of the switching MOS transistor; drain terminals of both the diode-connected transistor and the second MOS transistor are coupled to a source terminal of a third MOS transistor, the third MOS transistor coupled in series with a fourth MOS transistor; and a drain terminal of the fourth MOS transistor is coupled to ground. The third and fourth MOS transistors may be in series with the second MOS transistor. A gate terminal of the fourth transistor may be switched from ground to a supply voltage to activate the pull-down path.
-
-
-
-
-
-
-
-
-
Search Results
41
records
(took 0.019 seconds)
