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    Semiconductor package structure
    1.
    发明授权
    Semiconductor package structure 有权

    公开(公告)号：US12300679B2

    公开(公告)日：2025-05-13

    申请号：US17739295

    申请日：2022-05-09

    Applicant: MEDIATEK INC.

    Inventor： Yi-Jyun Lee ,  Duen-Yi Ho ,  Hsing-Chih Liu ,  Che-Hung Kuo

    IPC: H01L23/48 ,  H01L23/498 ,  H01L25/16 ,  H01L49/02 ,  H01L23/00

    Abstract: A semiconductor package structure includes a substrate, a redistribution layer, a first semiconductor die, and a first capacitor. The substrate has a wiring structure. The redistribution layer is disposed over the substrate. The first semiconductor die is disposed over the redistribution layer. The first capacitor is disposed in the substrate and is electrically coupled to the first semiconductor die. The first capacitor includes a first capacitor substrate, a plurality of first capacitor cells, and a first through via. The first capacitor substrate has a first top surface and a first bottom surface. The first capacitor cells are disposed in the first capacitor substrate. The first through via is disposed in the first capacitor substrate and electrically couples the first capacitor cells to the wiring structure on the first top surface and the first bottom surface.

    Semiconductor package structure
    2.
    发明授权
    Semiconductor package structure 有权

    公开(公告)号：US11710688B2

    公开(公告)日：2023-07-25

    申请号：US17363459

    申请日：2021-06-30

    Applicant: MEDIATEK INC.

    Inventor： Hsing-Chih Liu ,  Zheng Zeng ,  Che-Hung Kuo

    IPC: H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H01L23/48 ,  H01L25/065 ,  H01L23/31

    CPC classification number: H01L23/49811 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/5385 ,  H01L23/5389 ,  H01L25/0657 ,  H01L25/105

    Abstract: A semiconductor package structure includes a frontside redistribution layer, a stacking structure, a backside redistribution layer, a first intellectual property (IP) core, and a second IP core. The stacking structure is disposed over the frontside redistribution layer and comprises a first semiconductor die and a second semiconductor die over the first semiconductor die. The backside redistribution layer is disposed over the stacking structure. The first IP core is disposed in the stacking structure and is electrically coupled to the frontside redistribution layer through a first routing channel. The second IP core is disposed in the stacking structure and is electrically coupled to the backside redistribution layer through a second routing channel, wherein the second routing channel is separated from the first routing channel and electrically insulated from the frontside redistribution layer.

    Semiconductor package
    7.
    发明授权
    Semiconductor package 有权

    公开(公告)号：US11244913B2

    公开(公告)日：2022-02-08

    申请号：US16699851

    申请日：2019-12-02

    Applicant: MEDIATEK Inc.

    Inventor： Ying-Chih Chen ,  Yen-Ju Lu ,  Che-Ya Chou ,  Hsing-Chih Liu

    IPC: H01L23/66 ,  H01L23/31 ,  H01L23/528 ,  H01L23/532 ,  H01Q1/22

    Abstract: A semiconductor package includes a substrate, an electronic component, a dielectric layer a transmitting antenna, a receiving antenna and a FSS (Frequency selective surface) antenna. The electronic component is disposed on and electrically connected with the substrate. The dielectric layer has a dielectric upper surface. The transmitting antenna and the receiving antenna are formed adjacent to the substrate. The FSS antenna is formed adjacent to the dielectric upper surface of the dielectric layer. The FSS antenna is separated from the substrate by the dielectric layer in a wireless signal emitting direction.

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