公开(公告)号：US20210391343A1

公开(公告)日：2021-12-16

申请号：US16897556

申请日：2020-06-10

Applicant: Micron Technology, Inc.

Inventor： Michael Mutch ,  Sanket S. Kelkar ,  Ashonita A. Chavan ,  Sameer Chhajed ,  Adriel Jebin Jacob Jebaraj

IPC: H01L27/11507 ,  H01L27/1159 ,  H01L27/11504 ,  H01L27/11587 ,  H01L49/02

Abstract: Some embodiments include a capacitor having a container-shaped bottom portion. The bottom portion has a first region over a second region. The first region is thinner than the second region. The first region is a leaker region and the second region is a bottom electrode region. The bottom portion has an interior surface that extends along the first and second regions. An insulative material extends into the container shape. The insulative material lines the interior surface of the container shape. A conductive plug extends into the container shape and is adjacent the insulative material. A conductive structure extends across the conductive plug, the insulative material and the first region of the bottom portion. The conductive structure directly contacts the insulative material and the first region of the bottom portion, and is electrically coupled with the conductive plug. Some embodiments include methods of forming assemblies.

公开(公告)号：US20200312954A1

公开(公告)日：2020-10-01

申请号：US16369797

申请日：2019-03-29

Applicant: Micron Technology, Inc.

Inventor： Jerome A. Imonigie ,  Adriel Jebin Jacob Jebaraj ,  Brian J. Kerley ,  Sanjeev Sapra ,  Ashwin Panday

IPC: H01L49/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L27/108

Abstract: Methods, apparatuses, and systems related to forming a recess in a semiconductor structure are described. An example method includes etching the semiconductor structure using an elevated temperature dilution of acid and water. The method further includes etching the semiconductor structure using a room temperature wet etch of acid and water and a surface modification chemistry.

公开(公告)号：US11735549B2

公开(公告)日：2023-08-22

申请号：US17376934

申请日：2021-07-15

Applicant: Micron Technology, Inc.

Inventor： Suresh Yeruva ,  Owen R. Fay ,  Sameer S. Vadhavkar ,  Adriel Jebin Jacob Jebaraj ,  Wayne H. Huang

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/1146 ,  H01L2224/11614 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14517 ,  H01L2924/35121

Abstract: A method of manufacturing a semiconductor device having a conductive substrate having a first surface, a second surface opposite the first surface, and a passivation material covering a portion of the first surface can include applying a seed layer of conductive material to the first surface of the conductive substrate and to the passivation material, the seed layer having a first face opposite the conductive substrate. The method can include forming a plurality of pillars comprising layers of first and second materials. The method can include etching the seed layer to undercut the seed layer between the conductive substrate and the first material of at least one of the pillars. In some embodiments, a cross-sectional area of the seed layer in contact with the passivation material between the first material and the conductive substrate is less than the cross-sectional area of the second material.

公开(公告)号：US11587938B2

公开(公告)日：2023-02-21

申请号：US16897556

申请日：2020-06-10

Applicant: Micron Technology, Inc.

Inventor： Michael Mutch ,  Sanket S. Kelkar ,  Ashonita A. Chavan ,  Sameer Chhajed ,  Adriel Jebin Jacob Jebaraj

IPC: H01L27/11507 ,  H01L27/1159 ,  H01L49/02 ,  H01L27/11587 ,  H01L27/11504

Abstract: Some embodiments include a capacitor having a container-shaped bottom portion. The bottom portion has a first region over a second region. The first region is thinner than the second region. The first region is a leaker region and the second region is a bottom electrode region. The bottom portion has an interior surface that extends along the first and second regions. An insulative material extends into the container shape. The insulative material lines the interior surface of the container shape. A conductive plug extends into the container shape and is adjacent the insulative material. A conductive structure extends across the conductive plug, the insulative material and the first region of the bottom portion. The conductive structure directly contacts the insulative material and the first region of the bottom portion, and is electrically coupled with the conductive plug. Some embodiments include methods of forming assemblies.

公开(公告)号：US20210343670A1

公开(公告)日：2021-11-04

申请号：US17376934

申请日：2021-07-15

Applicant: Micron Technology, Inc.

Inventor： Suresh Yeruva ,  Owen R. Fay ,  Sameer S. Vadhavkar ,  Adriel Jebin Jacob Jebaraj ,  Wayne H. Huang

IPC: H01L23/00

Abstract: A method of manufacturing a semiconductor device having a conductive substrate having a first surface, a second surface opposite the first surface, and a passivation material covering a portion of the first surface can include applying a seed layer of conductive material to the first surface of the conductive substrate and to the passivation material, the seed layer having a first face opposite the conductive substrate. The method can include forming a plurality of pillars comprising layers of first and second materials. The method can include etching the seed layer to undercut the seed layer between the conductive substrate and the first material of at least one of the pillars. In some embodiments, a cross-sectional area of the seed layer in contact with the passivation material between the first material and the conductive substrate is less than the cross-sectional area of the second material.

公开(公告)号：US10978306B2

公开(公告)日：2021-04-13

申请号：US16369797

申请日：2019-03-29

Applicant: Micron Technology, Inc.

Inventor： Jerome A. Imonigie ,  Adriel Jebin Jacob Jebaraj ,  Brian J. Kerley ,  Sanjeev Sapra ,  Ashwin Panday

IPC: H01L21/306 ,  H01L49/02 ,  H01L21/311 ,  H01L27/108 ,  H01L21/3213 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/302

Abstract: Methods, apparatuses, and systems related to forming a recess in a semiconductor structure are described. An example method includes etching the semiconductor structure using an elevated temperature dilution of acid and water. The method further includes etching the semiconductor structure using a room temperature wet etch of acid and water and a surface modification chemistry.

公开(公告)号：US20240431095A1

公开(公告)日：2024-12-26

申请号：US18733586

申请日：2024-06-04

Applicant: Micron Technology, Inc.

Inventor： Yoshitaka Nakamura ,  Ashwin Panday ,  Iche Huang ,  Richard Beeler ,  Dojun Kim ,  Lane T. Cunningham ,  Adriel Jebin Jacob Jebaraj ,  Scott E. Sills

IPC: H10B12/00

Abstract: Methods, apparatuses, and systems related to a three-dimensional semiconductor device having a doped liner at least disposed between a capacitor and an access device. The doped liner may be configured to provide dopants that diffuse into a semiconductor path of the access device and improve an electrical connection between the access device and the capacitor.

公开(公告)号：US11081460B2

公开(公告)日：2021-08-03

申请号：US16236237

申请日：2018-12-28

Applicant: Micron Technology, Inc.

Inventor： Suresh Yeruva ,  Owen R. Fay ,  Sameer S. Vadhavkar ,  Adriel Jebin Jacob Jebaraj ,  Wayne H. Huang

IPC: H01L23/00

Abstract: A method of manufacturing a semiconductor device having a conductive substrate having a first surface, a second surface opposite the first surface, and a passivation material covering a portion of the first surface can include applying a seed layer of conductive material to the first surface of the conductive substrate and to the passivation material, the seed layer having a first face opposite the conductive substrate. The method can include forming a plurality of pillars comprising layers of first and second materials. The method can include etching the seed layer to undercut the seed layer between the conductive substrate and the first material of at least one of the pillars. In some embodiments, a cross-sectional area of the seed layer in contact with the passivation material between the first material and the conductive substrate is less than the cross-sectional area of the second material.

公开(公告)号：US20200211993A1

公开(公告)日：2020-07-02

申请号：US16236237

申请日：2018-12-28

Applicant: Micron Technology, Inc.

Inventor： Suresh Yeruva ,  Owen R. Fay ,  Sameer S. Vadhavkar ,  Adriel Jebin Jacob Jebaraj ,  Wayne H. Huang

IPC: H01L23/00

Abstract: A method of manufacturing a semiconductor device having a conductive substrate having a first surface, a second surface opposite the first surface, and a passivation material covering a portion of the first surface can include applying a seed layer of conductive material to the first surface of the conductive substrate and to the passivation material, the seed layer having a first face opposite the conductive substrate. The method can include forming a plurality of pillars comprising layers of first and second materials. The method can include etching the seed layer to undercut the seed layer between the conductive substrate and the first material of at least one of the pillars. In some embodiments, a cross-sectional area of the seed layer in contact with the passivation material between the first material and the conductive substrate is less than the cross-sectional area of the second material.