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公开(公告)号：US20220269598A1
公开(公告)日：2022-08-25
申请号：US17742896
申请日：2022-05-12
Applicant: Micron Technology, Inc.
Inventor： Paul Stonelake , Ning Chen , Fangfang Zhu , Alex Tang
Abstract: In an embodiment, a system includes a plurality of memory components that each include a plurality of management groups. Each management group includes a plurality of sub-groups. The system also includes a processing device that is operatively coupled with the plurality of memory components to perform wear-leveling operations that include maintaining a sub-group-level delta write count (DWC) for each of the sub-groups of each of the management groups of a memory component in the plurality of memory components. The wear-leveling operations also include determining, in connection with a write operation to a first sub-group of a first management group of the memory component, that a sub-group-level DWC for the first sub-group equals a management-group-move threshold, and responsively triggering a management-group-move operation from the first management group to a second management group of the memory component.
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公开(公告)号：US20210019088A1
公开(公告)日：2021-01-21
申请号：US16855470
申请日：2020-04-22
Applicant: Micron Technology, Inc.
Inventor： Fangfang Zhu , Ying Yu Tai , Ning Chen , Jiangli Zhu , Alex Tang
Abstract: Devices, methods, and media are described for unmap support in coarse mapped storage. In one embodiment a controller of a memory sub-system manages a set of metadata for super management units (SMU) of the memory sub-system, wherein each SMU of the memory sub-system comprises a plurality of data management units (MU), and wherein each MU comprises a plurality of addressable memory elements as part of a coarse memory storage of the memory sub-system. The controller processes a trim command for a first SMU of the plurality of SMUs, and adjusts a trim bit associated with metadata for the first SMU. This trim bit can then be used to manage read and write operations as the trimmed unit waits to be written with an unmap data pattern. Similarly, a trim bit in MU metadata can be used manage related operations to prevent memory access errors.
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公开(公告)号：US20230019910A1
公开(公告)日：2023-01-19
申请号：US17954023
申请日：2022-09-27
Applicant: Micron Technology, Inc.
Inventor： Fangfang Zhu , Ying Yu Tai , Ning Chen , Jiangli Zhu , Alex Tang
IPC: G06F3/06
Abstract: Embodiments include methods, systems, devices, instructions, and media for limiting hot-cold swap wear leveling in memory devices. In one embodiment, wear metric values are stored and monitored using multiple wear leveling criteria. The multiple wear leveling criteria include a hot-cold swap wear leveling criteria, which may make use of a write count offset value. Based on a first wear metric value of a first management group and a second wear metric value of a second management group, the first management group and the second management group are selected for a wear leveling swap operation. The wear leveling swap operation is performed with a whole management group read operation of the first management group to read a set of data, and a whole management group write operation to write the set of data to the second management group.
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公开(公告)号：US11481119B2
公开(公告)日：2022-10-25
申请号：US16874389
申请日：2020-05-14
Applicant: Micron Technology, Inc.
Inventor： Fangfang Zhu , Ying Yu Tai , Ning Chen , Jiangli Zhu , Alex Tang
Abstract: Embodiments include methods, systems, devices, instructions, and media for limiting hot-cold swap wear leveling in memory devices. In one embodiment, wear metric values are stored and monitored using multiple wear leveling criteria. The multiple wear leveling criteria include a hot-cold swap wear leveling criteria, which may make use of a write count offset value. Based on a first wear metric value of a first management group and a second wear metric value of a second management group, the first management group and the second management group are selected for a wear leveling swap operation. The wear leveling swap operation is performed with a whole management group read operation of the first management group to read a set of data, and a whole management group write operation to write the set of data to the second management group.
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公开(公告)号：US11360885B2
公开(公告)日：2022-06-14
申请号：US16797650
申请日：2020-02-21
Applicant: Micron Technology, Inc.
Inventor： Paul Stonelake , Ning Chen , Fangfang Zhu , Alex Tang
Abstract: In an embodiment, a system includes a plurality of memory components that each include a plurality of management groups. Each management group includes a plurality of sub-groups. The system also includes a processing device that is operatively coupled with the plurality of memory components to perform wear-leveling operations that include maintaining a sub-group-level delta write count (DWC) for each of the sub-groups of each of the management groups of a memory component in the plurality of memory components. The wear-leveling operations also include determining, in connection with a write operation to a first sub-group of a first management group of the memory component, that a sub-group-level DWC for the first sub-group equals a management-group-move threshold, and responsively triggering a management-group-move operation from the first management group to a second management group of the memory component.
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Patent Agency Ranking
公开(公告)号：US11216218B2
公开(公告)日：2022-01-04
申请号：US16855470
申请日：2020-04-22
Applicant: Micron Technology, Inc.
Inventor： Fangfang Zhu , Ying Yu Tai , Ning Chen , Jiangli Zhu , Alex Tang
Abstract: Devices, methods, and media are described for unmap support in coarse mapped storage. In one embodiment a controller of a memory sub-system manages a set of metadata for super management units (SMU) of the memory sub-system, wherein each SMU of the memory sub-system comprises a plurality of data management units (MU), and wherein each MU comprises a plurality of addressable memory elements as part of a coarse memory storage of the memory sub-system. The controller processes a trim command for a first SMU of the plurality of SMUs, and adjusts a trim bit associated with metadata for the first SMU. This trim bit can then be used to manage read and write operations as the trimmed unit waits to be written with an unmap data pattern. Similarly, a trim bit in MU metadata can be used manage related operations to prevent memory access errors.
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公开(公告)号：US12189960B2
公开(公告)日：2025-01-07
申请号：US17954023
申请日：2022-09-27
Applicant: Micron Technology, Inc.
Inventor： Fangfang Zhu , Ying Yu Tai , Ning Chen , Jiangli Zhu , Alex Tang
Abstract: Embodiments include methods, systems, devices, instructions, and media for limiting hot-cold swap wear leveling in memory devices. In one embodiment, wear metric values are stored and monitored using multiple wear leveling criteria. The multiple wear leveling criteria include a hot-cold swap wear leveling criteria, which may make use of a write count offset value. Based on a first wear metric value of a first management group and a second wear metric value of a second management group, the first management group and the second management group are selected for a wear leveling swap operation. The wear leveling swap operation is performed with a whole management group read operation of the first management group to read a set of data, and a whole management group write operation to write the set of data to the second management group.
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公开(公告)号：US11789861B2
公开(公告)日：2023-10-17
申请号：US17742896
申请日：2022-05-12
Applicant: Micron Technology, Inc.
Inventor： Paul Stonelake , Ning Chen , Fangfang Zhu , Alex Tang
CPC classification number: G06F12/0246 , G06F11/3037 , G06F12/0292 , G11C16/349 , G06F2212/7211
Abstract: In an embodiment, a system includes a plurality of memory components that each include a plurality of management groups. Each management group includes a plurality of sub-groups. The system also includes a processing device that is operatively coupled with the plurality of memory components to perform wear-leveling operations that include maintaining a sub-group-level delta write count (DWC) for each of the sub-groups of each of the management groups of a memory component in the plurality of memory components. The wear-leveling operations also include determining, in connection with a write operation to a first sub-group of a first management group of the memory component, that a sub-group-level DWC for the first sub-group equals a management-group-move threshold, and responsively triggering a management-group-move operation from the first management group to a second management group of the memory component.
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公开(公告)号：US11681472B2
公开(公告)日：2023-06-20
申请号：US17492181
申请日：2021-10-01
Applicant: Micron Technology, Inc.
Inventor： Fangfang Zhu , Ying Yu Tai , Ning Chen , Jiangli Zhu , Alex Tang
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0673 , G06F11/1004 , G06F13/1668
Abstract: Devices, methods, and media are described for unmap support in coarse mapped storage. In one embodiment a controller of a memory sub-system manages a set of metadata for super management units (SMU) of the memory sub-system, wherein each SMU of the memory sub-system comprises a plurality of data management units (MU), and wherein each MU comprises a plurality of addressable memory elements as part of a coarse memory storage of the memory sub-system. The controller processes a trim command for a first SMU of the plurality of SMUs, and adjusts a trim bit associated with metadata for the first SMU. This trim bit can then be used to manage read and write operations as the trimmed unit waits to be written with an unmap data pattern. Similarly, a trim bit in MU metadata can be used manage related operations to prevent memory access errors.
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公开(公告)号：US20220019383A1
公开(公告)日：2022-01-20
申请号：US17492181
申请日：2021-10-01
Applicant: Micron Technology, Inc.
Inventor： Fangfang Zhu , Ying Yu Tai , Ning Chen , Jiangli Zhu , Alex Tang
Abstract: Devices, methods, and media are described for unmap support in coarse mapped storage. In one embodiment a controller of a memory sub-system manages a set of metadata for super management units (SMU) of the memory sub-system, wherein each SMU of the memory sub-system comprises a plurality of data management units (MU), and wherein each MU comprises a plurality of addressable memory elements as part of a coarse memory storage of the memory sub-system. The controller processes a trim command for a first SMU of the plurality of SMUs, and adjusts a trim bit associated with metadata for the first SMU. This trim bit can then be used to manage read and write operations as the trimmed unit waits to be written with an unmap data pattern. Similarly, a trim bit in MU metadata can be used manage related operations to prevent memory access errors.
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