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    ELECTRONIC DEVICES INCLUDING FERROELECTRIC MATERIALS, AND RELATED MEMORY DEVICES
    1.
    发明申请
    ELECTRONIC DEVICES INCLUDING FERROELECTRIC MATERIALS, AND RELATED MEMORY DEVICES 有权

    公开(公告)号：US20250098175A1

    公开(公告)日：2025-03-20

    申请号：US18960091

    申请日：2024-11-26

    Applicant: Micron Technology, Inc.

    Inventor： Qian Tao ,  Matthew N. Rocklein ,  Beth R. Cook ,  D. V. Nirmal Ramaswamy

    IPC: H10B53/30 ,  H10N70/00 ,  H10N70/20

    Abstract: An electronic device comprises ferroelectric random access memory cells. One or more of the ferroelectric random access memory cells comprises a crystallized ferroelectric material and an electrode adjacent to the crystallized ferroelectric material. The crystallized ferroelectric material exhibits a dominant crystallographic orientation. The electrode comprises a crystalline material exhibiting an additional dominant crystallographic orientation inducing the dominant crystallographic orientation of the crystallized ferroelectric material. A memory device is also disclosed comprising an array of ferroelectric memory cells. The ferroelectric memory cell comprises a crystallized ferroelectric material having a first side and a second side opposite the first side, and an electrode adjacent the first side of the ferroelectric material. The crystallized ferroelectric material comprises a crystallized hafnium-based material exhibiting a dominant (200) crystallographic orientation. The electrode comprises a crystalline titanium nitride material formulated to induce the dominant (200) crystallographic orientation of the crystallized ferroelectric material.

    Methods Of Forming A Capacitor Comprising Ferroelectric Material And Including Current Leakage Paths Having Different Total Resistances
    4.
    发明申请
    Methods Of Forming A Capacitor Comprising Ferroelectric Material And Including Current Leakage Paths Having Different Total Resistances 审中-公开

    公开(公告)号：US20190355803A1

    公开(公告)日：2019-11-21

    申请号：US16527301

    申请日：2019-07-31

    Applicant: Micron Technology, Inc.

    Inventor： Muralikrishnan Balakrishnan ,  Beth R. Cook ,  Durai Vishak Nirmal Ramaswamy

    IPC: H01L49/02 ,  H01L27/11507

    Abstract: A memory cell comprises a capacitor having a first conductive capacitor electrode having laterally-spaced walls that individually have a top surface. A second conductive capacitor electrode is laterally between the walls of the first capacitor electrode, and comprises a portion above the first capacitor electrode. Ferroelectric material is laterally between the walls of the first capacitor electrode and laterally between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the ferroelectric material. A parallel current leakage path is between an elevationally-inner surface of the portion of the second capacitor electrode that is above the first capacitor electrode and at least one of the individual top surfaces of the laterally-spaced walls of the first capacitor electrode. The parallel current leakage path is circuit-parallel the intrinsic current leakage path and of lower total resistance than the intrinsic current leakage path. Other aspects, including methods, are disclosed.

    Methods of Incorporating Leaker Devices into Capacitor Configurations to Reduce Cell Disturb
    5.
    发明申请
    Methods of Incorporating Leaker Devices into Capacitor Configurations to Reduce Cell Disturb 审中-公开

    公开(公告)号：US20190189357A1

    公开(公告)日：2019-06-20

    申请号：US15843278

    申请日：2017-12-15

    Applicant: Micron Technology, Inc.

    Inventor： Ashonita A. Chavan ,  Beth R. Cook ,  Manuj Nahar ,  Durai Vishak Nirmal Ramaswamy

    IPC: H01G4/38 ,  G11C11/22 ,  H01L27/11507

    CPC classification number: H01G4/385 ,  G11C11/221 ,  H01L27/11507

    Abstract: Some embodiments include an apparatus having horizontally-spaced bottom electrodes supported by a supporting structure. Leaker device material is directly against the bottom electrodes. Insulative material is over the bottom electrodes, and upper electrodes are over the insulative material. Plate material extends across the upper electrodes and couples the upper electrodes to one another. The plate material is directly against the leaker device material. The leaker device material electrically couples the bottom electrodes to the plate material, and may be configured to discharge at least a portion of excess charge from the bottom electrodes to the plate material. Some embodiments include methods of forming apparatuses which include capacitors having bottom electrodes and top electrodes, with the top electrodes being electrically coupled to one another through a conductive plate. Leaker devices are formed to electrically couple the bottom electrodes to the conductive plate.

    SEMICONDUCTOR DEVICE STRUCTURES INCLUDING FERROELECTRIC MEMORY CELLS
    7.
    发明申请
    SEMICONDUCTOR DEVICE STRUCTURES INCLUDING FERROELECTRIC MEMORY CELLS 有权
    半导体器件结构包括电磁记忆体

    公开(公告)号：US20160064655A1

    公开(公告)日：2016-03-03

    申请号：US14936013

    申请日：2015-11-09

    Applicant: Micron Technology, Inc.

    Inventor： Qian Tao ,  Matthew N. Rocklein ,  Beth R. Cook ,  D.V. Nirmal Ramaswamy

    IPC: H01L45/00

    CPC classification number: H01L27/11507 ,  H01L28/60 ,  H01L45/04 ,  H01L45/1253 ,  H01L45/14 ,  H01L45/147 ,  H01L45/1608 ,  H01L45/1641

    Abstract: A method of forming a ferroelectric memory cell. The method comprises forming an electrode material exhibiting a desired dominant crystallographic orientation. A hafnium-based material is formed over the electrode material and the hafnium-based material is crystallized to induce formation of a ferroelectric material having a desired crystallographic orientation. Additional methods are also described, as are semiconductor device structures including the ferroelectric material.

    Abstract translation: 形成铁电存储单元的方法。 该方法包括形成显示出期望的主要晶体取向的电极材料。 在电极材料上形成铪基材料，并且铪基材料结晶以引起具有所需晶体取向的铁电材料的形成。 还描述了另外的方法，以及包括铁电材料的半导体器件结构。

    Methods Of Forming A Programmable Region That Comprises A Multivalent Metal Oxide Portion And An Oxygen Containing Dielectric Portion
    8.
    发明申请
    Methods Of Forming A Programmable Region That Comprises A Multivalent Metal Oxide Portion And An Oxygen Containing Dielectric Portion 有权
    形成包含多价金属氧化物部分的可编程区域和含有介电部分的氧气的方法

    公开(公告)号：US20140106534A1

    公开(公告)日：2014-04-17

    申请号：US14105623

    申请日：2013-12-13

    Applicant: Micron Technology, Inc.

    Inventor： D.V. Nirmal Ramaswamy ,  Beth R. Cook ,  Lei Bi ,  Wayne Huang ,  Ian C. Laboriante

    IPC: H01L45/00

    CPC classification number: H01L45/1608 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675

    Abstract: A method of forming a memory cell includes forming one of multivalent metal oxide material or oxygen-containing dielectric material over a first conductive structure. An outer surface of the multivalent metal oxide material or the oxygen-containing dielectric material is treated with an organic base. The other of the multivalent metal oxide material or oxygen-containing dielectric material is formed over the treated outer surface. A second conductive structure is formed over the other of the multivalent metal oxide material or oxygen-containing dielectric material.

    Abstract translation: 形成存储单元的方法包括在第一导电结构上形成多价金属氧化物材料或含氧电介质材料之一。 用有机碱处理多价金属氧化物材料或含氧电介质材料的外表面。 另外的多价金属氧化物材料或含氧电介质材料形成在经处理的外表面上。 在多价金属氧化物材料或含氧介电材料的另一个上形成第二导电结构。

    ELECTRONIC DEVICES INCLUDING CAPACITORS, AND RELATED METHODS
    9.
    发明申请
    ELECTRONIC DEVICES INCLUDING CAPACITORS, AND RELATED METHODS 有权

    公开(公告)号：US20250063737A1

    公开(公告)日：2025-02-20

    申请号：US18753940

    申请日：2024-06-25

    Applicant: Micron Technology, Inc.

    Inventor： Beth R. Cook ,  Zhuo Chen ,  Yixin Yan ,  Sarah P. Sredzinski ,  Gloria Y. Yang ,  Kathryn H. Russo

    IPC: H10B53/30

    Abstract: An electronic device comprises a memory array comprising access lines, data lines, and memory cells. Each memory cell is coupled to an associated access line and an associated data line and each memory cell comprises an access device, and a capacitor adjacent to the access device. The capacitor comprises a first electrode, a second electrode separated from the first electrode by an insulative material, and a leaker device adjacent to the first electrode. The second electrode and the leaker device extend through a lattice insulative material adjacent to the first electrode. The leaker device exhibits a substantially circular cross-sectional shape in a direction that is transverse to a direction in which the leaker device extends, with portions of the leaker device extending within a recessed region of the insulative material. Methods of forming electronic devices are also disclosed.

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