公开(公告)号：US20240004582A1

公开(公告)日：2024-01-04

申请号：US17853809

申请日：2022-06-29

Applicant: Micron Technology, Inc.

Inventor： Binbin Huo

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0652 ,  G06F3/0632 ,  G06F3/0688 ,  G06F3/0604

Abstract: The disclosure relates to improvements in command execution in semiconductor devices. In some aspects, the techniques described herein relate to an apparatus including: a storage array; and a processor configured to: receive a command from a host processor, start to profile the command by initializing a counter at a first time, issue the command to the storage array, receive a response to the command, end profiling of the command at a second time, and update a command timing for a type of the command.

公开(公告)号：US11360888B1

公开(公告)日：2022-06-14

申请号：US17176911

申请日：2021-02-16

Applicant: Micron Technology, Inc.

Inventor： Binbin Huo

IPC: G06F12/02 ,  G06F12/0882 ,  G06F12/0817 ,  G06F12/0873

Abstract: Various embodiments enable sending a notification to a host system based on an address mapping entry miss (or mismatch) on a memory sub-system, which can facilitate an update of one or more address mapping entries stored on the host system.

公开(公告)号：US20230335204A1

公开(公告)日：2023-10-19

申请号：US17659402

申请日：2022-04-15

Applicant: Micron Technology, Inc.

Inventor： Binbin Huo

IPC: G11C16/34 ,  G11C16/16 ,  G11C16/26

CPC classification number: G11C16/3445 ,  G11C16/16 ,  G11C16/26 ,  G11C16/349

Abstract: Methods, systems, and devices for techniques to retire unreliable blocks are described. A memory system may receive a request for information about a quantity of erase operations performed on a block of the memory system. Based on the request, the memory system may determine the quantity of erase operations performed on the block and transmit an indication of the quantity of erase operations performed on the block.

公开(公告)号：US20220300411A1

公开(公告)日：2022-09-22

申请号：US17714757

申请日：2022-04-06

Applicant: Micron Technology, Inc.

Inventor： Binbin Huo

IPC: G06F12/02 ,  G06F12/0882 ,  G06F13/16 ,  G06F12/0868

Abstract: Methods, systems, and devices for host side memory address management are described. In some examples, a host system may identify a read request that includes a logical address of a block of a memory device. The read request may be associated with a descriptor indicating a page of a cache of the host system. The host system may determine to assign a descriptor to a page of the cache, and may recycle one or more pages of the cache. In some examples, the host system may determine whether the page indicated by the descriptor includes a mapping between the logical address and a physical address of the memory device, and may issue a read command to the memory device based on the page including the mapping.

公开(公告)号：US20220164268A1

公开(公告)日：2022-05-26

申请号：US17529775

申请日：2021-11-18

Applicant: Micron Technology, Inc.

Inventor： Rainer F. Bonitz ,  Binbin Huo

IPC: G06F11/26 ,  G06F11/07 ,  G06F11/30 ,  G06F3/06

Abstract: A computing system can comprise a processing resource and a memory device coupled together via a first transmission link. The processing resource can be configured to test the first transmission link in response to the memory device failing to execute a command by sending the command to the memory device again for retry and monitoring the first transmission link for signals that indicate whether the command was executed by the memory device.

公开(公告)号：US20240176518A1

公开(公告)日：2024-05-30

申请号：US18388126

申请日：2023-11-08

Applicant: Micron Technology, Inc.

Inventor： Binbin Huo

IPC: G06F3/06

CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0679

Abstract: Methods, systems, and devices for parameter table protection for a memory system are described. Upon booting a memory system for a first time, the memory system or a host system may generate an error control code associated with parameter data stored to the memory system. The error control code may be stored to the memory system and may be configured to correct one or more errors in the parameter data upon subsequent boot sequences of the memory system. Accordingly, upon booting the memory system for a second or a subsequent time, the error control code may be used to identify and correct errors in the parameter data, which may reduce the quantity of copies of parameter data stored to the memory system and may prevent the memory system from experiencing a system crash.

公开(公告)号：US11861191B2

公开(公告)日：2024-01-02

申请号：US17500676

申请日：2021-10-13

Applicant: Micron Technology, Inc.

Inventor： Binbin Huo

IPC: G06F3/06

CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0679

Abstract: Methods, systems, and devices for parameter table protection for a memory system are described. Upon booting a memory system for a first time, the memory system or a host system may generate an error control code associated with parameter data stored to the memory system. The error control code may be stored to the memory system and may be configured to correct one or more errors in the parameter data upon subsequent boot sequences of the memory system. Accordingly, upon booting the memory system for a second or a subsequent time, the error control code may be used to identify and correct errors in the parameter data, which may reduce the quantity of copies of parameter data stored to the memory system and may prevent the memory system from experiencing a system crash.

公开(公告)号：US11816028B2

公开(公告)日：2023-11-14

申请号：US17714757

申请日：2022-04-06

Applicant: Micron Technology, Inc.

Inventor： Binbin Huo

IPC: G06F12/02 ,  G06F12/0882 ,  G06F13/16 ,  G06F12/0868

CPC classification number: G06F12/0246 ,  G06F12/0868 ,  G06F12/0882 ,  G06F13/1668 ,  G06F2212/7201

Abstract: Methods, systems, and devices for host side memory address management are described. In some examples, a host system may identify a read request that includes a logical address of a block of a memory device. The read request may be associated with a descriptor indicating a page of a cache of the host system. The host system may determine to assign a descriptor to a page of the cache, and may recycle one or more pages of the cache. In some examples, the host system may determine whether the page indicated by the descriptor includes a mapping between the logical address and a physical address of the memory device, and may issue a read command to the memory device based on the page including the mapping.

公开(公告)号：US20220308993A1

公开(公告)日：2022-09-29

申请号：US17838832

申请日：2022-06-13

Applicant: Micron Technology, Inc.

Inventor： Binbin Huo

IPC: G06F12/02 ,  G06F12/0882 ,  G06F12/0817 ,  G06F12/0873

Abstract: Various embodiments enable sending a notification to a host system based on an address mapping entry miss (or mismatch) on a memory sub-system, which can facilitate an update of one or more address mapping entries stored on the host system.

公开(公告)号：US12242745B2

公开(公告)日：2025-03-04

申请号：US18388126

申请日：2023-11-08

Applicant: Micron Technology, Inc.

Inventor： Binbin Huo

IPC: G06F3/06

Abstract: Methods, systems, and devices for parameter table protection for a memory system are described. Upon booting a memory system for a first time, the memory system or a host system may generate an error control code associated with parameter data stored to the memory system. The error control code may be stored to the memory system and may be configured to correct one or more errors in the parameter data upon subsequent boot sequences of the memory system. Accordingly, upon booting the memory system for a second or a subsequent time, the error control code may be used to identify and correct errors in the parameter data, which may reduce the quantity of copies of parameter data stored to the memory system and may prevent the memory system from experiencing a system crash.