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    MEMORY DEVICE SECURITY AND ROW HAMMER MITIGATION
    5.
    发明申请
    MEMORY DEVICE SECURITY AND ROW HAMMER MITIGATION 有权

    公开(公告)号：US20240411466A1

    公开(公告)日：2024-12-12

    申请号：US18808887

    申请日：2024-08-19

    Applicant: Micron Technology, Inc.

    Inventor： Yang Lu ,  Sujeet Ayyapureddi ,  Edmund J. Gieske ,  Cagdas Dirik ,  Ameen D. Akel ,  Elliott C. Cooper-Balis ,  Amitava Majumdar ,  Robert M. Walker ,  Danilo Caraccio

    IPC: G06F3/06

    Abstract: Systems, methods, and apparatus for memory device security and row hammer mitigation are described. A control mechanism may be implemented in a front-end and/or a back-end of a memory sub-system to refresh rows of the memory. A row activation command having a row address at control circuitry of a memory sub-system and incrementing a first count of a row counter corresponding to the row address stored in a content addressable memory (CAM) of the memory sub-system may be received. Control circuitry may determine whether the first count is greater than a row hammer threshold (RHT) minus a second count of a CAM decrease counter (CDC); the second count may be incremented each time the CAM is full. A refresh command to the row address may be issued when a determination is made that the first count is greater than the RHT minus the second count.

    Interleaved cache prefetching
    6.
    发明授权
    Interleaved cache prefetching 有权

    公开(公告)号：US11886348B2

    公开(公告)日：2024-01-30

    申请号：US18117820

    申请日：2023-03-06

    Applicant: Micron Technology, Inc.

    Inventor： Laurent Isenegger ,  Robert M. Walker ,  Cagdas Dirik

    IPC: G06F3/06 ,  G06F12/0862 ,  G06F12/0831

    CPC classification number: G06F12/0862 ,  G06F3/061 ,  G06F3/0658 ,  G06F3/0683 ,  G06F12/0835 ,  G06F2212/283

    Abstract: A method includes receiving, at a direct memory access (DMA) controller of a memory device, a first command from a first cache controller coupled to the memory device to prefetch first data from the memory device and sending the prefetched first data, in response to receiving the first command, to a second cache controller coupled to the memory device. The method can further include receiving a second command from a second cache controller coupled to the memory device to prefetch second data from the memory device, and sending the prefetched second data, in response to receiving the second command, to a third cache controller coupled to the memory device.

    DYNAMICALLY SIZED REDUNDANT WRITE BUFFER WITH SECTOR-BASED TRACKING
    8.
    发明申请
    DYNAMICALLY SIZED REDUNDANT WRITE BUFFER WITH SECTOR-BASED TRACKING 有权

    公开(公告)号：US20210357332A1

    公开(公告)日：2021-11-18

    申请号：US16876967

    申请日：2020-05-18

    Applicant: Micron Technology, Inc.

    Inventor： Cagdas Dirik ,  Robert M. Walker

    IPC: G06F12/0891 ,  G06F12/0893 ,  G06F12/0815 ,  G06F13/16 ,  G06F11/07 ,  G06F11/30

    Abstract: Exemplary methods, apparatuses, and systems include detecting an operation to write dirty data to a cache. The cache is divided into a plurality of channels. In response to the operation, the dirty data is written to a first cache line in the cache, the first cache line being accessed via a first channel. Additionally, a redundant copy of the dirty data is written to a second cache line in the cache. The second cache line serves as a redundant write buffer and is accessed via a second channel, the first and second channels differing from one another. A metadata entry for the second cache line is updated to reference a location of the dirty data in the first cache line.

    CACHE BUFFER
    9.
    发明申请
    CACHE BUFFER 审中-公开

    公开(公告)号：US20190065373A1

    公开(公告)日：2019-02-28

    申请号：US15690442

    申请日：2017-08-30

    Applicant: Micron Technology, Inc.

    Inventor： Cagdas Dirik ,  Robert M. Walker

    IPC: G06F12/0831 ,  G06F13/16

    Abstract: The present disclosure includes apparatuses and methods related to a cache buffer. An example apparatus can store data associated with a request in one of a number of buffers and service a subsequent request for data associated with the request using the one of the number of buffers. The subsequent request can be serviced while the request is being serviced by the cache controller.

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