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    Host clock effective delay range extension
    3.
    发明授权
    Host clock effective delay range extension 有权

    公开(公告)号：US11042301B2

    公开(公告)日：2021-06-22

    申请号：US16219218

    申请日：2018-12-13

    Applicant: Micron Technology, Inc.

    Inventor： Claudio Giaccio ,  Erminio Di Martino ,  Jeffery Carlos Bell

    IPC: G06F1/12 ,  H04L5/00 ,  G06F3/06 ,  G06F11/10

    Abstract: Devices and techniques are disclosed herein for applying an effective sampling delay at a host device to one of an input signal, such as from an embedded MultiMediaCard (eMMC) device, or a clock signal. The host device can apply a configurable delay to one of the input signal or the clock signal with respect to a first edge of the clock signal, sample the input signal using the clock signal according to the configurable delay, and selectively align the sampled input signal to a subsequent, second edge of the clock signal to extend the configurable delay of the host device.

    OPTIMIZING A MEMORY SUB-SYSTEM PARTITION CONFIGURATION USING SIMULATION
    6.
    发明公开
    OPTIMIZING A MEMORY SUB-SYSTEM PARTITION CONFIGURATION USING SIMULATION 审中-公开

    公开(公告)号：US20240281155A1

    公开(公告)日：2024-08-22

    申请号：US18582525

    申请日：2024-02-20

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Angelo della Monica ,  Luca Dorato ,  Claudio Giaccio ,  Massimo Iaculo

    IPC: G06F3/06

    CPC classification number: G06F3/0625 ,  G06F3/0659 ,  G06F3/0679

    Abstract: A set of simulations of a function to be performed by a computing system is performed. Each of the set of simulations are performed according to a distinct hardware/software partition configuration for the computing system. One or more outputs of each simulation of the set of simulations are obtained. The one or more outputs of a respective simulation indicate resources consumed by the computing system based on the respective simulation. An optimal hardware/software partition configuration for the computing system is determined based on the obtained one or more outputs of each simulation of the set of simulations. An indication of the determined optimal hardware/software partition configuration is provided to a processing device to cause the processing device to execute one or more operations associated with the function at the computing system in accordance with the optimal hardware/software partition configuration.

    HOST CLOCK EFFECTIVE DELAY RANGE EXTENSION
    7.
    发明申请
    HOST CLOCK EFFECTIVE DELAY RANGE EXTENSION 有权

    公开(公告)号：US20210286516A1

    公开(公告)日：2021-09-16

    申请号：US17331281

    申请日：2021-05-26

    Applicant: Micron Technology, Inc.

    Inventor： Claudio Giaccio ,  Erminio Di Martino ,  Jeffery Carlos Bell

    IPC: G06F3/06 ,  G06F11/10

    Abstract: Devices and techniques are disclosed herein to extend a range of an effective delay of a delay circuit having a configurable delay limited to a first range of delay values with respect to a first edge of a clock signal. A selection circuit can selectively apply the configurable delay to a subsequent, second edge of the clock signal to extend the range of the effective delay of the delay circuit beyond the first range of delay values.

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