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    Data recovery within a memory sub-system without moving or processing the data through a host
    2.
    发明授权
    Data recovery within a memory sub-system without moving or processing the data through a host 有权

    公开(公告)号：US11068365B2

    公开(公告)日：2021-07-20

    申请号：US16110881

    申请日：2018-08-23

    Applicant: Micron Technology, Inc.

    Inventor： David G. Springberg

    IPC: G06F11/20 ,  G06F3/06

    Abstract: A command to transfer data in a portion of a memory component to a recovery portion of a different memory component is received from a host system, wherein the portion of the memory component is associated with a portion of the memory component that has failed, and the data in the portion of the memory component is recovered and transferred to the recovery portion of the different memory component without moving or processing the data through the host system responsive to receipt of the command.

    Two-stage hybrid memory buffer for multiple streams
    3.
    发明授权
    Two-stage hybrid memory buffer for multiple streams 有权

    公开(公告)号：US11829638B2

    公开(公告)日：2023-11-28

    申请号：US17537446

    申请日：2021-11-29

    Applicant: Micron Technology, Inc.

    Inventor： David G. Springberg ,  David Sluiter

    IPC: G06F3/06 ,  G06F11/10 ,  G11C29/52 ,  H03M13/11 ,  G06F12/02

    CPC classification number: G06F3/0656 ,  G06F3/0619 ,  G06F3/0685 ,  G06F11/1068 ,  G06F12/0253 ,  G11C29/52 ,  H03M13/1102 ,  G06F2212/1044 ,  G06F2212/7205

    Abstract: Described herein is a system comprising one or more external dynamic random access memory (DRAM) devices having a first programming unit buffer and a second programming unit buffer, an internal static RAM (SRAM) device, one or more non-volatile memory (NVM) devices, and a processing device, operatively coupled with the one or more external DRAM devices, the internal SRAM device, and the one or more NVM devices. The processing device transfers first write data from the first programming unit buffer to the internal SRAM device responsive to the first write data satisfying a programming unit (PU) threshold, the PU threshold pertaining to a PU of the one or more NVM devices. The processing device also writes the first write data from the internal SRAM device as a first programming unit to the one or more NVM devices, and transfers a second write data from the second programming unit buffer to the internal SRAM device responsive to the second write data satisfying the PU threshold. The processing device further writes the second write data from the internal SRAM device as a second programming unit to the one or more NVM devices.

    DATA RECOVERY WITHIN A MEMORY SUB-SYSTEM
    4.
    发明申请
    DATA RECOVERY WITHIN A MEMORY SUB-SYSTEM 有权

    公开(公告)号：US20210342236A1

    公开(公告)日：2021-11-04

    申请号：US17376283

    申请日：2021-07-15

    Applicant: Micron Technology, Inc.

    Inventor： David G. Springberg

    IPC: G06F11/20

    Abstract: A command to transfer data in a portion of a memory component to a recovery portion of a different memory component is received from a host system, wherein the portion of the memory component is associated with a portion of the memory component that has failed, and the data in the portion of the memory component is recovered and transferred to the recovery portion of the different memory component without moving or processing the data through the host system responsive to receipt of the command.

    MEMORY CHANNEL CONTROLLER OPERATION
    5.
    发明申请
    MEMORY CHANNEL CONTROLLER OPERATION 有权

    公开(公告)号：US20230060322A1

    公开(公告)日：2023-03-02

    申请号：US17464576

    申请日：2021-09-01

    Applicant: Micron Technology, Inc.

    Inventor： David G. Springberg

    IPC: G06F3/06

    Abstract: The present disclosure includes systems, apparatuses, and methods related to memory channel controller operation. For example, a data type associated with an access request may be determined. The access request may be executed by utilizing, responsive to determining the access request is associated with a first data type, a first memory channel controller coupled to a first memory device to access a first memory address range, associated with the first data type, allocated to the first memory device. The access request may be executed by utilizing, responsive to determining the access request is associated with a second data type, the first memory channel controller and a second memory channel controller coupled to a second memory device to access a second memory address range, associated with the second data type, allocated among the first memory device and the second memory device.

    Two-stage hybrid memory buffer for multiple streams
    6.
    发明授权
    Two-stage hybrid memory buffer for multiple streams 有权

    公开(公告)号：US11188250B2

    公开(公告)日：2021-11-30

    申请号：US16171073

    申请日：2018-10-25

    Applicant: Micron Technology, Inc.

    Inventor： David G. Springberg ,  David Sluiter

    IPC: G06F12/00 ,  G06F3/06 ,  G06F11/10 ,  G11C29/52 ,  H03M13/11 ,  G06F12/02

    Abstract: Described herein are embodiments related to a two-stage hybrid memory buffer for multiple streams in memory sub-systems. A processing device determines that first write data of a first stream stored in a host buffer component satisfies a threshold to program a first programming unit. The processing device transfers the first write data to the staging buffer component from the host buffer component, and writes the first write data from the staging buffer component as the first programming unit to a first die of multiple non-volatile memory (NVM) dies. The processing device determines that second write data of a second stream satisfies a threshold to program a second programming unit, transfers the second write data to the staging buffer component from the host buffer component, and writes the second write data from the staging buffer component as the second programming unit to a second die of the multiple NVM dies.

    MEMORY CHANNEL CONTROLLER OPERATION
    7.
    发明公开
    MEMORY CHANNEL CONTROLLER OPERATION 审中-公开

    公开(公告)号：US20240256152A1

    公开(公告)日：2024-08-01

    申请号：US18635535

    申请日：2024-04-15

    Applicant: Micron Technology, Inc.

    Inventor： David G. Springberg

    IPC: G06F3/06

    CPC classification number: G06F3/0622 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0659 ,  G06F3/0679

    Abstract: The present disclosure includes systems, apparatuses, and methods related to memory channel controller operation. For example, a data type associated with an access request may be determined. The access request may be executed by utilizing, responsive to determining the access request is associated with a first data type, a first memory channel controller coupled to a first memory device to access a first memory address range, associated with the first data type, allocated to the first memory device. The access request may be executed by utilizing, responsive to determining the access request is associated with a second data type, the first memory channel controller and a second memory channel controller coupled to a second memory device to access a second memory address range, associated with the second data type, allocated among the first memory device and the second memory device.

    DATA RECOVERY WITHIN A MEMORY SUB-SYSTEM
    9.
    发明申请
    DATA RECOVERY WITHIN A MEMORY SUB-SYSTEM 审中-公开

    公开(公告)号：US20200065204A1

    公开(公告)日：2020-02-27

    申请号：US16110881

    申请日：2018-08-23

    Applicant: Micron Technology, Inc.

    Inventor： David G. Springberg

    IPC: G06F11/20

    Abstract: A command to transfer data in a portion of a memory component to a recovery portion of a different memory component is received from a host system, wherein the portion of the memory component is associated with a portion of the memory component that has failed, and the data in the portion of the memory component is recovered and transferred to the recovery portion of the different memory component without moving or processing the data through the host system responsive to receipt of the command.

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