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    Methods of forming a semiconductor device
    1.
    发明授权
    Methods of forming a semiconductor device 有权

    公开(公告)号：US11239240B2

    公开(公告)日：2022-02-01

    申请号：US16902783

    申请日：2020-06-16

    Applicant: Micron Technology, Inc.

    Inventor： Arzum F. Simsek-Ege ,  Guangjun Yang ,  Kuo-Chen Wang ,  Mohd Kamran Akhtar ,  Katsumi Koge

    IPC: G11C11/24 ,  H01L27/108 ,  H01L21/764 ,  G11C11/408 ,  G11C11/4091

    Abstract: A semiconductor device comprises semiconductive pillars; digit lines laterally between the semiconductive pillars; nitride caps vertically overlying the digit lines; nitride structures overlying surfaces of the nitride caps; redistribution material structures comprising upper portions overlying upper surfaces of the nitride caps and the nitride structures, and lower portions overlying upper surfaces of the semiconductive pillars; a low-K dielectric material laterally between the digit lines and the semiconductive pillars; air gaps laterally between the low-K dielectric material and the semiconductive pillars, and having upper boundaries below the upper surfaces of the nitride caps; and a nitride dielectric material laterally between the air gaps and the semiconductive pillars. Memory devices, electronic systems, and method of forming a semiconductor device are also described.

    Integrated Assemblies Having Dielectric Regions Along Conductive Structures, and Methods of Forming Integrated Assemblies
    4.
    发明申请
    Integrated Assemblies Having Dielectric Regions Along Conductive Structures, and Methods of Forming Integrated Assemblies 审中-公开

    公开(公告)号：US20190378843A1

    公开(公告)日：2019-12-12

    申请号：US16419978

    申请日：2019-05-22

    Applicant: Micron Technology, Inc.

    Inventor： Guangjun Yang ,  Mohd Kamran Akhtar ,  Silvia Borsari ,  Alex J. Schrinsky

    IPC: H01L27/108

    Abstract: Some embodiments include a method of forming an integrated assembly. A construction is formed to include a conductive structure having a top surface, and a pair of sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface, and rails are along the sidewall surfaces. The rails include sacrificial material. The sacrificial material is removed to leave openings. Sealant material is formed to extend within the openings. The sealant material has a lower dielectric constant than the insulative material. Some embodiments include an integrated assembly having a conductive structure with a top surface and a pair of opposing sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface. Voids are along the sidewall surfaces and are capped by sealant material. The sealant material has a lower dielectric constant than the insulative material.

    SULFUR DIOXIDE ETCH CHEMISTRIES
    5.
    发明申请
    SULFUR DIOXIDE ETCH CHEMISTRIES 审中-公开
    硫化二氧化氯化学

    公开(公告)号：US20150307778A1

    公开(公告)日：2015-10-29

    申请号：US14790401

    申请日：2015-07-02

    Applicant: Micron Technology, Inc.

    Inventor： Guangjun Yang

    IPC: C09K13/00

    CPC classification number: C09K13/00 ,  C09K13/04 ,  C23F1/10 ,  C23F1/12 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31138

    Abstract: Methods of forming a semiconductor device structure and sulfur dioxide etch chemistries. The methods and chemistries, which may be plasma chemistries, include use of sulfur dioxide and a halogen-based compound to form a trimmed pattern of a patterning material, such as a resist material, at a critical dimension with low feature width roughness, with low space width roughness, without excessive height loss, and without substantial irregularities in the elevational profile, as compared to trimmed features formed using conventional chemistries and trimming methods.

    Abstract translation: 形成半导体器件结构和二氧化硫蚀刻化学品的方法。 可以是等离子体化学的方法和化学物质包括使用二氧化硫和卤素类化合物在具有低特征宽度粗糙度的临界尺寸下形成诸如抗蚀剂材料的图案形成材料的修剪图案，具有低的 与使用常规化学和修整方法形成的修剪特征相比，空间宽度粗糙度没有过高的高度损失，并且没有显着的不规则性。

    Memory circuitry and method used in forming memory circuitry
    6.
    发明授权
    Memory circuitry and method used in forming memory circuitry 有权

    公开(公告)号：US11785762B2

    公开(公告)日：2023-10-10

    申请号：US17364154

    申请日：2021-06-30

    Applicant: Micron Technology, Inc.

    Inventor： Guangjun Yang

    IPC: H10B12/00

    CPC classification number: H10B12/34 ,  H10B12/0335 ,  H10B12/053 ,  H10B12/315 ,  H10B12/482

    Abstract: A method used in forming memory circuitry comprises forming transistors individually comprising one source/drain region and another source/drain region. A channel region is between the one and the another source/drain regions. A conductive gate is operatively proximate the channel region. Conductive vias are formed that are individually directly electrically coupled to the another source/drain region. Conductor material is formed that is directly coupled to the one source/drain region. The conductor material is patterned in one direction to form horizontal lines of the conductor material that have a horizontal trench between immediately-adjacent of the horizontal conductor-material lines. In a self-aligned manner, digitlines are formed that are individually in individual of the trenches between the immediately-adjacent conductor-material lines. After forming the digitlines, the conductor material is patterned in another direction that is horizontally angled from the one direction to form conductor vias that are individually directly electrically coupled to the one source/drain region. A plurality of storage elements is formed that are individually directly electrically coupled to individual of the conductor vias. Other aspects, including structure independent of method, are disclosed.

    Integrated assemblies having dielectric regions along conductive structures, and methods of forming integrated assemblies
    7.
    发明授权
    Integrated assemblies having dielectric regions along conductive structures, and methods of forming integrated assemblies 有权

    公开(公告)号：US10700073B2

    公开(公告)日：2020-06-30

    申请号：US16419978

    申请日：2019-05-22

    Applicant: Micron Technology, Inc.

    Inventor： Guangjun Yang ,  Mohd Kamran Akhtar ,  Silvia Borsari ,  Alex J. Schrinsky

    IPC: H01L27/108

    Abstract: Some embodiments include a method of forming an integrated assembly. A construction is formed to include a conductive structure having a top surface, and a pair of sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface, and rails are along the sidewall surfaces. The rails include sacrificial material. The sacrificial material is removed to leave openings. Sealant material is formed to extend within the openings. The sealant material has a lower dielectric constant than the insulative material. Some embodiments include an integrated assembly having a conductive structure with a top surface and a pair of opposing sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface. Voids are along the sidewall surfaces and are capped by sealant material. The sealant material has a lower dielectric constant than the insulative material.

    Integrated assemblies having spacers of low permittivity along digit-lines, and methods of forming integrated assemblies
    8.
    发明授权
    Integrated assemblies having spacers of low permittivity along digit-lines, and methods of forming integrated assemblies 有权

    公开(公告)号：US10546862B1

    公开(公告)日：2020-01-28

    申请号：US16248584

    申请日：2019-01-15

    Applicant: Micron Technology, Inc.

    Inventor： Guangjun Yang ,  Suraj J. Mathew

    IPC: H01L27/108 ,  H01L21/768

    Abstract: Some embodiments include an integrated assembly having active-region-pillars extending upwardly from a base. Each of the active-region-pillars has a pair of storage-element-contact-regions, and a digit-line-contact-region between the storage-element-contact-regions. The integrated assembly includes, along a cross-section, a first digit-line-contact-region adjacent a first storage-element-contact-region. The first digit-line-contact-region is recessed relative to the first storage-element-contact-region. A first digit-line is coupled with the first digit-line-contact-region. A second digit-line is laterally offset from the first digit-line. An insulative material is between the first digit-line and the first storage-element-contact-region. A cup-shaped indentation extends into the insulative material and the first storage-element-contact-region. Insulative spacers are along sidewalls of the first and second digit-lines, and include first material. First and second insulative pillars are over the first and second digit-lines, and include second material. Some embodiments include methods of forming integrated assemblies.

    Methods of forming integrated assemblies having dielectric regions along conductive structures
    9.
    发明授权
    Methods of forming integrated assemblies having dielectric regions along conductive structures 有权

    公开(公告)号：US10347643B1

    公开(公告)日：2019-07-09

    申请号：US16002890

    申请日：2018-06-07

    Applicant: Micron Technology, Inc.

    Inventor： Guangjun Yang ,  Mohd Kamran Akhtar ,  Silvia Borsari ,  Alex J. Schrinsky

    IPC: H01L27/108

    Abstract: Some embodiments include a method of forming an integrated assembly. A construction is formed to include a conductive structure having a top surface, and a pair of sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface, and rails are along the sidewall surfaces. The rails include sacrificial material. The sacrificial material is removed to leave openings. Sealant material is formed to extend within the openings. The sealant material has a lower dielectric constant than the insulative material. Some embodiments include an integrated assembly having a conductive structure with a top surface and a pair of opposing sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface. Voids are along the sidewall surfaces and are capped by sealant material. The sealant material has a lower dielectric constant than the insulative material.

    Methods of sealing openings, and methods of forming integrated assemblies
    10.
    发明授权
    Methods of sealing openings, and methods of forming integrated assemblies 有权

    公开(公告)号：US10290534B1

    公开(公告)日：2019-05-14

    申请号：US16007361

    申请日：2018-06-13

    Applicant: Micron Technology, Inc.

    Inventor： Guangjun Yang

    IPC: H01L21/76 ,  H01L21/764 ,  H01L21/02 ,  H01L27/108

    Abstract: Some embodiments include a method of forming an integrated assembly. A construction is formed to include a structure having an exposed surface, and to include an opening proximate the structure. An aperture extends into the opening. A first material is deposited to form a mass along the exposed surface of the structure. Particles are sputtered from the mass and across the aperture. The particles agglomerate to form a sealant material which traps a void within the opening.

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