公开(公告)号：US20240069768A1

公开(公告)日：2024-02-29

申请号：US17897940

申请日：2022-08-29

Applicant: Micron Technology, Inc.

Inventor： Marco Redaelli

IPC: G06F3/06

CPC classification number: G06F3/0632 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679

Abstract: A memory device controller for a non-volatile memory device can be configured to allow exclusive access to initiate or increment a refresh routine based on an earlier-received one of a refresh command from a host device or an interval-triggered refresh command from the controller. The memory device controller can be configured to lock out access to the refresh routine from a later-received one of the refresh command from the host device or the interval-triggered refresh command from the controller. The memory device controller can release a lock on access to the refresh routine upon completion of a block refresh routine for a memory block of the memory device. In some examples, the refresh command from the host device can be based on a power cycle status of the host device.

公开(公告)号：US20240078037A1

公开(公告)日：2024-03-07

申请号：US17939628

申请日：2022-09-07

Applicant: Micron Technology, Inc.

Inventor： Gaurav Sinha ,  Marco Redaelli ,  Shivamurthy Shastri

IPC: G06F3/06 ,  H04L67/10

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0679 ,  H04L67/10

Abstract: Methods, systems, and devices for multi-host communications are described. In some examples, a memory system may be coupled with multiple host systems. The memory system may facilitate communications between the multiple host systems For example, a first host system may be coupled with a first buffer of the memory system and a second host system may be coupled with a second buffer of the memory system. The first host system may have read and write access to the first buffer and read access to the second buffer. In response to a write operation being initiated by the first host system, data may be written to the first buffer. The second host system may read the data written to the first buffer. The second host system may take an action or respond based on the data read from the first buffer.

公开(公告)号：US20190286505A1

公开(公告)日：2019-09-19

申请号：US16007191

申请日：2018-06-13

Applicant: Micron Technology, Inc.

Inventor： Marco Redaelli

IPC: G06F11/07

Abstract: An example apparatus includes a first memory and a second memory coupled to the first memory. A controller may be coupled to the first memory and the second memory. The controller may be configured to cause the apparatus to be initialized by executing instructions on the first memory device. Initializing the apparatus may include operating the apparatus according to a set of semantics different than a set of semantics used by the second memory device. The controller may be configured to cause a determination regarding at least one health characteristic of the second memory to be made subsequent to the apparatus being initialized.

公开(公告)号：US20240354005A1

公开(公告)日：2024-10-24

申请号：US18644821

申请日：2024-04-24

Applicant: Micron Technology, Inc.

Inventor： Daniela Ruggeri ,  Fabrizio Fiorenza ,  Marco Redaelli ,  Francesco Lupo

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0679

Abstract: Various examples are directed to systems and methods involving a managed NAND non-volatile memory device comprising a memory array and a memory controller. The memory controller may receive a verification request from a requesting device, the verification request comprising an indication of a first portion of the memory array, and a first known check value. The memory controller may apply an operation based at least in part on first data from the first portion of the memory array to generate a calculated check value and determine verification result data based at least in part on the first known check value and the calculated check value.

公开(公告)号：US12112060B2

公开(公告)日：2024-10-08

申请号：US17939628

申请日：2022-09-07

Applicant: Micron Technology, Inc.

Inventor： Gaurav Sinha ,  Marco Redaelli ,  Shivamurthy Shastri

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0679

Abstract: Methods, systems, and devices for multi-host communications are described. In some examples, a memory system may be coupled with multiple host systems. The memory system may facilitate communications between the multiple host systems For example, a first host system may be coupled with a first buffer of the memory system and a second host system may be coupled with a second buffer of the memory system. The first host system may have read and write access to the first buffer and read access to the second buffer. In response to a write operation being initiated by the first host system, data may be written to the first buffer. The second host system may read the data written to the first buffer. The second host system may take an action or respond based on the data read from the first buffer.

公开(公告)号：US20240160566A1

公开(公告)日：2024-05-16

申请号：US18383746

申请日：2023-10-25

Applicant: Micron Technology, Inc.

Inventor： Marco Redaelli

IPC: G06F12/02 ,  G06F11/07

CPC classification number: G06F12/0292 ,  G06F11/0772 ,  G06F12/0246 ,  G06F2212/7201

Abstract: A memory sub-system with multiple flash translation layer (FTL) tables is disclosed. A host system can utilize a memory sub-system that includes one or more memory components. The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system. The FTL provides several services, including translating logical addresses used by the host to physical addresses used to access physical memory. If one FTL table is corrupted, the logical-to-physical mapping of another FTL table may be used, allowing the device to continue to provide read-write access to at least a portion of the memory sub-system. Thus, by use of a secondary FTL table, the reliability of the memory sub-system is improved.

公开(公告)号：US10817363B2

公开(公告)日：2020-10-27

申请号：US16007191

申请日：2018-06-13

Applicant: Micron Technology, Inc.

Inventor： Marco Redaelli

IPC: G06F11/00 ,  G06F11/07

Abstract: An example apparatus includes a first memory and a second memory coupled to the first memory. A controller may be coupled to the first memory and the second memory. The controller may be configured to cause the apparatus to be initialized by executing instructions on the first memory device. Initializing the apparatus may include operating the apparatus according to a set of semantics different than a set of semantics used by the second memory device. The controller may be configured to cause a determination regarding at least one health characteristic of the second memory to be made subsequent to the apparatus being initialized.

公开(公告)号：US20250147846A1

公开(公告)日：2025-05-08

申请号：US18776211

申请日：2024-07-17

Applicant: Micron Technology, Inc.

Inventor： Marco Redaelli ,  Gaurav Sinha ,  Zhang Lei

IPC: G06F11/10 ,  G06F11/07

Abstract: Methods, systems, and devices for sorting retired blocks of non-volatile memory cells are described. A memory system may recover a block that has been marked as “bad” using a requalification process. For example, after operating in an error protection mode for the block, the memory system may monitor the block to determine whether a status flag indicating an access error is set. If the status flag is set, the memory system may store information that indicates the block is unrecoverable, and the block may subsequently be retired. Alternatively, if a status flag is not set, the memory system may store information that indicates the block may be recoverable. If one or more additional access operations to the block are successful, the memory system may store information that indicates the block may be used for subsequent access operations.

公开(公告)号：US20210027853A1

公开(公告)日：2021-01-28

申请号：US16521977

申请日：2019-07-25

Applicant: Micron Technology, Inc.

Inventor： Marco Redaelli

IPC: G11C29/38 ,  G06F13/40 ,  F16H61/12 ,  B60R1/00

Abstract: An example system includes a processing resource and a switch board coupled to a system under test (SUT) and the processing resource. The SUT includes a memory device. The switch board can be configured to provide power to the SUT, communicate a first signal from the SUT to the processing resource, and provide a second signal to the SUT that simulates an input to the SUT during operation of the SUT. The processing resource can be configured to receive a function, selected from a library of functions, to execute during a test of the memory device and cause the switch board to provide the second signal during the test of the SUT.

公开(公告)号：US20250013384A1

公开(公告)日：2025-01-09

申请号：US18888111

申请日：2024-09-17

Applicant: Micron Technology, Inc.

Inventor： Gaurav Sinha ,  Marco Redaelli ,  Shivamurthy Shastri

IPC: G06F3/06

Abstract: Methods, systems, and devices for multi-host communications are described. In some examples, a memory system may be coupled with multiple host systems. The memory system may facilitate communications between the multiple host systems For example, a first host system may be coupled with a first buffer of the memory system and a second host system may be coupled with a second buffer of the memory system. The first host system may have read and write access to the first buffer and read access to the second buffer. In response to a write operation being initiated by the first host system, data may be written to the first buffer. The second host system may read the data written to the first buffer. The second host system may take an action or respond based on the data read from the first buffer.