-
公开(公告)号：US11704024B2
公开(公告)日：2023-07-18
申请号：US16947291
申请日：2020-07-27
Applicant: Micron Technology, Inc.
Inventor： Ying Yu Tai , Ning Chen , Jiangli Zhu
CPC classification number: G06F3/0616 , G06F3/065 , G06F3/0659 , G06F3/0679 , G06F12/10 , G06F2212/1036 , G06F2212/202 , G06F2212/657
Abstract: A memory sub-system performs a first media management operation among a plurality of individual data units of a memory device after a first interval, the first media management operation comprising a first algebraic mapping function, and performs a second media management operation among a first plurality of groups of data units of the memory device after a second interval, wherein a first group of the first plurality of groups comprises the plurality of individual data units, the second media management operation comprising a second algebraic mapping function.
-
公开(公告)号：US20230019910A1
公开(公告)日：2023-01-19
申请号：US17954023
申请日：2022-09-27
Applicant: Micron Technology, Inc.
Inventor： Fangfang Zhu , Ying Yu Tai , Ning Chen , Jiangli Zhu , Alex Tang
IPC: G06F3/06
Abstract: Embodiments include methods, systems, devices, instructions, and media for limiting hot-cold swap wear leveling in memory devices. In one embodiment, wear metric values are stored and monitored using multiple wear leveling criteria. The multiple wear leveling criteria include a hot-cold swap wear leveling criteria, which may make use of a write count offset value. Based on a first wear metric value of a first management group and a second wear metric value of a second management group, the first management group and the second management group are selected for a wear leveling swap operation. The wear leveling swap operation is performed with a whole management group read operation of the first management group to read a set of data, and a whole management group write operation to write the set of data to the second management group.
-
公开(公告)号：US11481119B2
公开(公告)日：2022-10-25
申请号：US16874389
申请日：2020-05-14
Applicant: Micron Technology, Inc.
Inventor： Fangfang Zhu , Ying Yu Tai , Ning Chen , Jiangli Zhu , Alex Tang
Abstract: Embodiments include methods, systems, devices, instructions, and media for limiting hot-cold swap wear leveling in memory devices. In one embodiment, wear metric values are stored and monitored using multiple wear leveling criteria. The multiple wear leveling criteria include a hot-cold swap wear leveling criteria, which may make use of a write count offset value. Based on a first wear metric value of a first management group and a second wear metric value of a second management group, the first management group and the second management group are selected for a wear leveling swap operation. The wear leveling swap operation is performed with a whole management group read operation of the first management group to read a set of data, and a whole management group write operation to write the set of data to the second management group.
-
公开(公告)号：US11080132B2
公开(公告)日：2021-08-03
申请号：US16510559
申请日：2019-07-12
Applicant: Micron Technology, Inc.
Abstract: A request to store a first data is received. The first data and a first error-checking data are received. The first error-checking data can be based on a cyclic redundancy check (CRC) operation of the first data. A second data is generated by removing a portion of the first data. A second error-checking data of the second data is generated by using the first error-checking data and the removed portion of the first data.
-
公开(公告)号：US20210011799A1
公开(公告)日：2021-01-14
申请号：US16510559
申请日：2019-07-12
Applicant: Micron Technology, Inc.
Abstract: A request to store a first data is received. The first data and a first error-checking data are received. The first error-checking data can be based on a cyclic redundancy check (CRC) operation of the first data. A second data is generated by removing a portion of the first data. A second error-checking data of the second data is generated by using the first error-checking data and the removed portion of the first data.
-
Patent Agency Ranking
公开(公告)号：US20200110544A1
公开(公告)日：2020-04-09
申请号：US16153016
申请日：2018-10-05
Applicant: Micron Technology, Inc.
Inventor： Fangfang Zhu , Jiangli Zhu , Ning Chen , Ying Yu Tai
Abstract: Data is copied, from a second group of data blocks in a second plurality of groups of data blocks that are mapped, to a first group of data blocks in a first set of groups of data blocks that are not mapped to include the first group of data blocks in the second set of groups of data blocks that are mapped. A sub-total write counter associated with the first group of data blocks is reset. A value of the sub-total write counter indicates a number of write operations performed on the first group of data blocks since the first group of data blocks has been included in the second set of groups of data blocks. A wear leveling operation is performed on the first group of data blocks based on the sub-total write counter.
-
公开(公告)号：US12298847B2
公开(公告)日：2025-05-13
申请号：US18299532
申请日：2023-04-12
Applicant: Micron Technology, Inc.
Inventor： Seungjune Jeon , Juane Li , Ning Chen
IPC: G06F11/10
Abstract: A request to write host data to a memory device of a memory sub-system is received. Redundancy metadata associated with the host data is generated. A determination of a first status associated with the host data is made. The redundancy metadata associated with the host data is updated to indicate at least the first status associated with the host data. A memory access operation is performed to write the host data and the updated redundancy metadata to the memory device.
-
公开(公告)号：US11880600B2
公开(公告)日：2024-01-23
申请号：US17446746
申请日：2021-09-02
Applicant: Micron Technology, Inc.
Inventor： Ning Chen , Jiangli Zhu , Yi-Min Lin , Fangfang Zhu
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0679
Abstract: A write request directed to the non-volatile memory device is received. A stripe associated with an address specified by the write request is present in the volatile memory device is determined. The volatile memory device includes a plurality of stripes, each stripe of the plurality of stripes having a plurality of managed units. The write request on a managed unit of the stripe in the volatile memory device is performed. The stripe in the volatile memory device is evicted to a stripe in the non-volatile memory device.
-
公开(公告)号：US20230251927A1
公开(公告)日：2023-08-10
申请号：US18299532
申请日：2023-04-12
Applicant: Micron Technology, Inc.
Inventor： Seungjune Jeon , Juane Li , Ning Chen
IPC: G06F11/10
CPC classification number: G06F11/1004 , G06F11/1068
Abstract: A request to write host data to a memory device of a memory sub-system is received. Redundancy metadata associated with the host data is generated. A determination of a first status associated with the host data is made. The redundancy metadata associated with the host data is updated to indicate at least the first status associated with the host data. A memory access operation is performed to write the host data and the updated redundancy metadata to the memory device.
-
公开(公告)号：US11687363B2
公开(公告)日：2023-06-27
申请号：US16855510
申请日：2020-04-22
Applicant: Micron Technology, Inc.
Inventor： Fangfang Zhu , Ying Yu Tai , Ning Chen , Jiangli Zhu , Wei Wang
CPC classification number: G06F9/4881 , G06F3/0659 , G06F5/06 , G06F9/5016 , G06F9/546 , G06F11/3037 , G06F11/3409 , G06F11/3433 , G06F13/1673 , G06F13/1694 , G06F2201/81 , G06F2209/5022
Abstract: In one embodiment, a processing device is coupled to memory components to monitor host read operations and host write operations from a host device coupled to the plurality of memory components. The processing device schedules, using a variable size internal command queue, a predetermined proportion of back-end processing device read and write operations as internal management traffic proportional to a number of the host read operations and a number of the host write operations. The processing device then executes a subset of the host read operations and the host write operations. Following execution of the subset of the host read operations and the host write operations, the processing device executes an internal management traffic operation based on the predetermined proportion.
-
-
-
-
-
-
-
-
-
Search Results
56
records
(took 0.024 seconds)
