公开(公告)号：US11442656B2

公开(公告)日：2022-09-13

申请号：US17182077

申请日：2021-02-22

Applicant: Micron Technology, Inc.

Inventor： Horia C. Simionescu ,  Rohitkumar Makhija ,  Peng-Cheng Chen ,  Jung Sheng Hoei

IPC: G06F3/06

Abstract: An indication that one or more program operations have been interrupted as a result of a read operation can be received at a first controller component associated with a memory sub-system. Context data associated with interrupted program operations can be received at the first controller component. A control sequence based on the context data can be generated at the first controller component. The control sequence can indicate how a second controller component associated with the memory sub-system interacts with a memory component of the memory sub-system to perform the read operation and to resume the interrupted program operations. The control sequence can further specify one or more additional operations that are associated with copying data of the interrupted program operations between first and second memory locations of the memory component. The control sequence can be provided to the second controller component.

公开(公告)号：US20230297511A1

公开(公告)日：2023-09-21

申请号：US18124447

申请日：2023-03-21

Applicant: Micron Technology, Inc.

Inventor： Jiangang Wu ,  Qisong Lin ,  Jung Sheng Hoei ,  Yunqiu Wan ,  Ashutosh Malshe ,  Peng-Cheng Chen

IPC: G06F12/0891 ,  G06F12/0811 ,  G06F12/02 ,  G06F12/0882 ,  G06F11/14

CPC classification number: G06F12/0891 ,  G06F12/0811 ,  G06F12/0246 ,  G06F12/0882 ,  G06F11/14 ,  G11C16/06

Abstract: Methods, systems, and devices for full multi-plane operation enablement are described. A flash controller can determine that a first plane of a set of planes of a memory die is an invalid plane. The flash controller can issue a single descriptor associated with a multi-plane operation for the set of planes of the memory die. The single descriptor can include a plurality of commands for the multi-plane operation in which the first command of the plurality of commands can be a duplicate of a second command of the plurality of commands based on the first plane being the invalid plane. In some cases, a negative-and (NAND) controller can receive the single descriptor associated with the multi-plane operation for the set of planes of a memory die. The NAND controller can issue a plurality of commands for the multi-plane operation based on receiving the single descriptor.

公开(公告)号：US11803321B2

公开(公告)日：2023-10-31

申请号：US17943113

申请日：2022-09-12

Applicant: Micron Technology, Inc.

Inventor： Horia C. Simionescu ,  Rohitkumar Makhija ,  Peng-Cheng Chen ,  Jung Sheng Hoei

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: A method can include receiving, by a first controller component of a memory sub-system, a read operation, responsive to receiving the read operation, interrupting, by the first controller component, one or more program operations being performed by the memory sub-system, receiving, by the first controller component, a control sequence from a second controller component, wherein the control sequence is based on context data associated with the interrupted one or more program operations, and performing, by the first controller component, the control sequence by copying data of the interrupted one or more program operations from a first memory location to a second memory location of a memory component associated with the memory sub-system, and performing the read operation.

公开(公告)号：US20200210098A1

公开(公告)日：2020-07-02

申请号：US16235474

申请日：2018-12-28

Applicant: Micron Technology, Inc.

Inventor： Horia C. Simionescu ,  Rohitkumar Makhija ,  Peng-Cheng Chen ,  Jung Sheng Hoei

IPC: G06F3/06

Abstract: A read operation can be received while one or more program operations are being performed at a memory sub-system. In response to receiving the read operation, the one or more program operations being performed at the memory sub-system can be interrupted. Context data associated with the one or more interrupted program operations can be determined and the context data can be provided to a firmware associated with the memory sub-system. A control sequence can be received from the firmware based on the context data. The read operation can be performed and the one or more interrupted program operations can be resumed based on the control sequence from the firmware.

公开(公告)号：US12001340B2

公开(公告)日：2024-06-04

申请号：US18124447

申请日：2023-03-21

Applicant: Micron Technology, Inc.

Inventor： Jiangang Wu ,  Qisong Lin ,  Jung Sheng Hoei ,  Yunqiu Wan ,  Ashutosh Malshe ,  Peng-Cheng Chen

IPC: G06F11/00 ,  G06F11/14 ,  G06F12/02 ,  G06F12/0811 ,  G06F12/0882 ,  G06F12/0891 ,  G06F13/16 ,  G11C16/06

CPC classification number: G06F12/0891 ,  G06F11/14 ,  G06F12/0246 ,  G06F12/0811 ,  G06F12/0882 ,  G06F13/1668 ,  G11C16/06

Abstract: Methods, systems, and devices for full multi-plane operation enablement are described. A flash controller can determine that a first plane of a set of planes of a memory die is an invalid plane. The flash controller can issue a single descriptor associated with a multi-plane operation for the set of planes of the memory die. The single descriptor can include a plurality of commands for the multi-plane operation in which the first command of the plurality of commands can be a duplicate of a second command of the plurality of commands based on the first plane being the invalid plane. In some cases, a negative-and (NAND) controller can receive the single descriptor associated with the multi-plane operation for the set of planes of a memory die. The NAND controller can issue a plurality of commands for the multi-plane operation based on receiving the single descriptor.

公开(公告)号：US20210173585A1

公开(公告)日：2021-06-10

申请号：US17182077

申请日：2021-02-22

Applicant: Micron Technology, Inc.

Inventor： Horia C. Simionescu ,  Rohitkumar Makhija ,  Peng-Cheng Chen ,  Jung Sheng Hoei

IPC: G06F3/06

Abstract: An indication that one or more program operations have been interrupted as a result of a read operation can be received at a first controller component associated with a memory sub-system. Context data associated with interrupted program operations can be received at the first controller component. A control sequence based on the context data can be generated at the first controller component. The control sequence can indicate how a second controller component associated with the memory sub-system interacts with a memory component of the memory sub-system to perform the read operation and to resume the interrupted program operations. The control sequence can further specify one or more additional operations that are associated with copying data of the interrupted program operations between first and second memory locations of the memory component. The control sequence can be provided to the second controller component.

公开(公告)号：US11615029B2

公开(公告)日：2023-03-28

申请号：US16730881

申请日：2019-12-30

Applicant: Micron Technology, Inc.

Inventor： Jiangang Wu ,  Qisong Lin ,  Jung Sheng Hoei ,  Yunqiu Wan ,  Ashutosh Malshe ,  Peng-Cheng Chen

IPC: G06F11/00 ,  G06F12/0891 ,  G06F12/0811 ,  G06F12/02 ,  G06F12/0882 ,  G06F11/14 ,  G11C16/06 ,  G06F13/16

Abstract: Methods, systems, and devices for full multi-plane operation enablement are described. A flash controller can determine that a first plane of a set of planes of a memory die is an invalid plane. The flash controller can issue a single descriptor associated with a multi-plane operation for the set of planes of the memory die. The single descriptor can include a plurality of commands for the multi-plane operation in which the first command of the plurality of commands can be a duplicate of a second command of the plurality of commands based on the first plane being the invalid plane. In some cases, a negative-and (NAND) controller can receive the single descriptor associated with the multi-plane operation for the set of planes of a memory die. The NAND controller can issue a plurality of commands for the multi-plane operation based on receiving the single descriptor.

公开(公告)号：US20210200682A1

公开(公告)日：2021-07-01

申请号：US16730881

申请日：2019-12-30

Applicant: Micron Technology, Inc.

Inventor： Jiangang Wu ,  Qisong Lin ,  Jung Sheng Hoei ,  Yunqiu Wan ,  Ashutosh Malshe ,  Peng-Cheng Chen

IPC: G06F12/0891 ,  G06F12/0882 ,  G06F12/02 ,  G06F12/0811

Abstract: Methods, systems, and devices for full multi-plane operation enablement are described. A flash controller can determine that a first plane of a set of planes of a memory die is an invalid plane. The flash controller can issue a single descriptor associated with a multi-plane operation for the set of planes of the memory die. The single descriptor can include a plurality of commands for the multi-plane operation in which the first command of the plurality of commands can be a duplicate of a second command of the plurality of commands based on the first plane being the invalid plane. In some cases, a negative-and (NAND) controller can receive the single descriptor associated with the multi-plane operation for the set of planes of a memory die. The NAND controller can issue a plurality of commands for the multi-plane operation based on receiving the single descriptor.

公开(公告)号：US10929056B2

公开(公告)日：2021-02-23

申请号：US16235474

申请日：2018-12-28

Applicant: Micron Technology, Inc.

Inventor： Horia C. Simionescu ,  Rohitkumar Makhija ,  Peng-Cheng Chen ,  Jung Sheng Hoei

IPC: G06F3/06

Abstract: A read operation can be received while one or more program operations are being performed at a memory sub-system. In response to receiving the read operation, the one or more program operations being performed at the memory sub-system can be interrupted. Context data associated with the one or more interrupted program operations can be determined and the context data can be provided to a firmware associated with the memory sub-system. A control sequence can be received from the firmware based on the context data. The read operation can be performed and the one or more interrupted program operations can be resumed based on the control sequence from the firmware.