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公开(公告)号：US20210257008A1
公开(公告)日：2021-08-19
申请号：US17175999
申请日：2021-02-15
Applicant: Micron Technology, Inc.
Inventor： Koji Sakui , Peter Sean Feeley
Abstract: Some embodiments include apparatuses and methods for activating a signal associated with an access line coupled to different groups of memory cells during a memory operation of a device, and for sensing data lines of the device during different time intervals of the memory operation to determine the value of information stored in the memory cells. Each of the data lines can be coupled to a respective memory cell of each of the groups of memory cells. In at least one of such apparatuses and methods, the signal applied to the access line can remain activated during the memory operation.
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公开(公告)号：US10936392B2
公开(公告)日：2021-03-02
申请号：US16234256
申请日：2018-12-27
Applicant: Micron Technology, Inc.
Inventor： Jung Sheng Hoei , Peter Sean Feeley , Sampath K. Ratnam , Sead Zildzic , Kishore Kumar Muchherla
Abstract: A processing device in a memory system receives a memory command indicating a read window size and a first read voltage and identifies a read window for a first data block of the memory component having the read window size and centered at the first read voltage. The processing device determines whether a number of bit flips for the first data block within the read window exceeds an error threshold and, in response to the number of bit flips exceeding the error threshold, refreshes data stored on the first data block of the memory component.
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公开(公告)号：US10777284B2
公开(公告)日：2020-09-15
申请号：US16782720
申请日：2020-02-05
Applicant: Micron Technology, Inc.
Inventor： Ashutosh Malshe , Kishore Kumar Muchherla , Harish Reddy Singidi , Peter Sean Feeley , Sampath Ratnam , Kulachet Tanpairoj , Ting Luo
Abstract: Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.
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公开(公告)号：US20200176063A1
公开(公告)日：2020-06-04
申请号：US16782720
申请日：2020-02-05
Applicant: Micron Technology, Inc.
Inventor： Ashutosh Malshe , Kishore Kumar Muchherla , Harish Reddy Singidi , Peter Sean Feeley , Sampath Ratnam , Kulachet Tanpairoj , Ting Luo
Abstract: Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.
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公开(公告)号：US20190333585A1
公开(公告)日：2019-10-31
申请号：US16504039
申请日：2019-07-05
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Sampath Ratnam , Preston Allen Thomson , Harish Reddy Singidi , Jung Sheng Hoei , Peter Sean Feeley , Jianmin Huang
Abstract: Devices and techniques for NAND temperature data management are disclosed herein. A command to write data to a NAND component in the NAND device is received at a NAND controller of the NAND device. A temperature corresponding to the NAND component is obtained in response to receiving the command. The command is then executed to write data to the NAND component and to write a representation of the temperature. The data is written to a user portion and the representation of the temperature is written to a management portion that is accessible only to the controller and segregated from the user portion.
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Patent Agency Ranking
公开(公告)号：US10347344B2
公开(公告)日：2019-07-09
申请号：US15689747
申请日：2017-08-29
Applicant: Micron Technology, Inc.
Inventor： Ashutosh Malshe , Kishore Kumar Muchherla , Harish Singidi , Peter Sean Feeley , Sampath Ratnam , Kulachet Tanpairoj , Ting Luo
Abstract: Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.
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公开(公告)号：US20150333001A1
公开(公告)日：2015-11-19
申请号：US14810044
申请日：2015-07-27
Applicant: Micron Technology, Inc.
Inventor： Koji Sakui , Peter Sean Feeley , Akira Goda
IPC: H01L23/528 , H01L29/49 , H01L23/532 , H01L23/535 , G11C11/56 , H01L27/115
CPC classification number: H01L23/528 , G11C11/5671 , G11C16/0483 , H01L23/53214 , H01L23/53228 , H01L23/535 , H01L27/11529 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L29/4975 , H01L2924/0002 , H01L2924/00
Abstract: Apparatuses and methods are disclosed, including an apparatus with rows of vertical strings of memory cells coupled to a common source and multiple data lines associated with each row of vertical strings. Each data line associated with a row is coupled to at least one of the vertical strings in the row. Additional apparatuses and methods are described.
Abstract translation: 公开了装置和方法，包括具有耦合到公共源的存储器单元的垂直串行的装置和与每行垂直串相关联的多个数据线的装置。 与行相关联的每个数据行被耦合到行中的至少一个垂直字符串。 描述附加的装置和方法。
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公开(公告)号：US20210287748A1
公开(公告)日：2021-09-16
申请号：US17331395
申请日：2021-05-26
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Sampath Ratnam , Preston Allen Thomson , Harish Reddy Singidi , Jung Sheng Hoei , Peter Sean Feeley , Jianmin Huang
Abstract: Devices and techniques for NAND temperature data management are disclosed herein. A command to write data to a NAND component in the NAND device is received at a NAND controller of the NAND device. A temperature corresponding to the NAND component is obtained in response to receiving the command. The command is then executed to write data to the NAND component and to write a representation of the temperature. The data is written to a user portion and the representation of the temperature is written to a management portion that is accessible only to the controller and segregated from the user portion.
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公开(公告)号：US11106577B2
公开(公告)日：2021-08-31
申请号：US16175005
申请日：2018-10-30
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Peter Sean Feeley , Sampath K. Ratnam , Ashutosh Malshe , Christopher S. Hale
IPC: G06F12/128 , G06F12/02 , G06F12/0897
Abstract: An amount of valid data for each data block of multiple data blocks stored at a first memory is determined. An operation to write valid data of a particular data block from the first memory to a second memory is performed based on the amount of valid data for each data block. A determination is made that a threshold condition associated with when valid data of the data blocks was written to the first memory has been satisfied. In response to determining that the threshold condition has been satisfied, the operation to write valid data of the data blocks from the first memory to the second memory is performed based on when the valid data was written to the first memory.
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公开(公告)号：US20210117318A1
公开(公告)日：2021-04-22
申请号：US17247805
申请日：2020-12-23
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Sampath K. Ratnam , Ashutosh Malshe , Peter Sean Feeley
IPC: G06F12/02
Abstract: A processing device in a memory system determines a rate at which an amount of valid data is decreasing on a first block of the memory device and determines whether the rate at which the amount of valid data is decreasing on the first block satisfies a threshold criterion. Responsive to the rate at which the amount of valid data is decreasing on the first block satisfying the threshold criterion, the processing device performs a media management operation on the first block of the memory device.
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