公开(公告)号：US20150179822A1

公开(公告)日：2015-06-25

申请号：US14641439

申请日：2015-03-09

Applicant: NANYA TECHNOLOGY CORP.

Inventor： Shian-Jyh Lin

IPC: H01L29/792 ,  H01L27/108

CPC classification number: H01L29/792 ,  H01L27/108 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10891

Abstract: A semiconductor device capable of reducing influences of adjacent word lines is provided in the present invention. The semiconductor device includes: a substrate, and a word line disposed in the substrate. The word line includes: a gate electrode, a gate dielectric layer disposed between the gate electrode and the substrate and at least one first charge trapping dielectric layer disposed adjacent to the gate electrode, wherein the first charge trapping dielectric layer comprises HfO2, TiO2, ZrO2, a germanium nanocrystal layer, an organic charge trapping material, HfSiOxNy, or MoSiOqNz.

Abstract translation: 本发明提供能够减少相邻字线的影响的半导体装置。 半导体器件包括：衬底和设置在衬底中的字线。 字线包括：栅电极，设置在栅极电极和衬底之间的栅介质层和邻近栅电极设置的至少一个第一电荷俘获电介质层，其中第一电荷俘获电介质层包括HfO 2，TiO 2，ZrO 2 锗纳米晶层，有机电荷俘获材料，HfSiOxNy或MoSiOqNz。

公开(公告)号：US09214571B2

公开(公告)日：2015-12-15

申请号：US14641439

申请日：2015-03-09

Applicant: NANYA TECHNOLOGY CORP.

Inventor： Shian-Jyh Lin

IPC: H01L29/792 ,  H01L27/108

CPC classification number: H01L29/792 ,  H01L27/108 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10891

Abstract: A semiconductor device capable of reducing influences of adjacent word lines is provided in the present invention. The semiconductor device includes: a substrate, and a word line disposed in the substrate. The word line includes: a gate electrode, a gate dielectric layer disposed between the gate electrode and the substrate and at least one first charge trapping dielectric layer disposed adjacent to the gate electrode, wherein the first charge trapping dielectric layer comprises HfO2, TiO2, ZrO2, a germanium nanocrystal layer, an organic charge trapping material, HfSiOxNy, or MoSiOqNz.

公开(公告)号：US09779957B2

公开(公告)日：2017-10-03

申请号：US14447634

申请日：2014-07-31

Applicant: NANYA TECHNOLOGY CORP.

Inventor： Shian-Jyh Lin ,  Jeng-Ping Lin ,  Chin-Piao Chang ,  Jen-Jui Huang

IPC: H01L21/76 ,  H01L21/308 ,  H01L21/762

CPC classification number: H01L21/3081 ,  H01L21/76224

Abstract: A method of manufacturing a semiconductor structure. A patterned first hard mask is formed on a substrate. The patterned first hard mask includes first trench patterns extending along a first direction. A second hard mask is then formed on the patterned first hard mask. A patterned photoresist layer is formed on the second hard mask. The patterned photoresist layer includes second trench patterns extending along a second direction. The second trench patterns intersect first trench patterns. Using the patterned photoresist layer as an etch mask, a first etch process is performed to transfer the second trench patterns into the patterned first hard mask and the second hard mask. Subsequently, using the patterned first hard mask as an etch mask, a second etch process is performed to transfer the first trench patterns and the second trench patterns into the substrate.

公开(公告)号：US20140342567A1

公开(公告)日：2014-11-20

申请号：US14447634

申请日：2014-07-31

Applicant: NANYA TECHNOLOGY CORP.

Inventor： Shian-Jyh Lin ,  Jeng-Ping Lin ,  Chin-Piao Chang ,  Jen-Jui Huang

IPC: H01L21/308

CPC classification number: H01L21/3081 ,  H01L21/76224

Abstract: A method of manufacturing a semiconductor structure. A patterned first hard mask is formed on a substrate. The patterned first hard mask includes first trench patterns extending along a first direction. A second hard mask is then formed on the patterned first hard mask. A patterned photoresist layer is formed on the second hard mask. The patterned photoresist layer includes second trench patterns extending along a second direction. The second trench patterns intersect first trench patterns. Using the patterned photoresist layer as an etch mask, a first etch process is performed to transfer the second trench patterns into the patterned first hard mask and the second hard mask. Subsequently, using the patterned first hard mask as an etch mask, a second etch process is performed to transfer the first trench patterns and the second trench patterns into the substrate.

Abstract translation: 一种制造半导体结构的方法。 在基板上形成图案化的第一硬掩模。 图案化的第一硬掩模包括沿着第一方向延伸的第一沟槽图案。 然后在图案化的第一硬掩模上形成第二硬掩模。 在第二硬掩模上形成图案化的光致抗蚀剂层。 图案化的光致抗蚀剂层包括沿着第二方向延伸的第二沟槽图案。 第二沟槽图案与第一沟槽图案相交。 使用图案化的光致抗蚀剂层作为蚀刻掩模，执行第一蚀刻工艺以将第二沟槽图案转印到图案化的第一硬掩模和第二硬掩模中。 随后，使用图案化的第一硬掩模作为蚀刻掩模，执行第二蚀刻工艺以将第一沟槽图案和第二沟槽图案转移到衬底中。