公开(公告)号：US20240221852A1

公开(公告)日：2024-07-04

申请号：US18402549

申请日：2024-01-02

Applicant: Netlist, Inc.

Inventor： Hyun Lee ,  Jayesh R. Bhakta ,  Soonju Choi

IPC: G11C29/10 ,  G11C29/12 ,  G11C5/04

CPC classification number: G11C29/10 ,  G11C29/12 ,  G11C5/04

Abstract: A memory module comprises memory devices, a data module and a control module. The memory module is operable in a first mode in which at least some of the memory devices are accessed by a system memory controller in a computer system for memory read and/or write operations at a memory access speed, the control module is configured to register address and control signals associated with the memory read and/or write operations, and the data module is configured to propagate data signals between the at least some of the memory devices and the memory controller. The memory module is further operable in a second mode in which the memory devices are not accessed by the system memory controller for memory read or write operations, and the data module is configured to communicate data signals with at least some of the memory devices at the memory access speed.

公开(公告)号：US20210271593A1

公开(公告)日：2021-09-02

申请号：US17202021

申请日：2021-03-15

Applicant: Netlist, Inc.

Inventor： Hyun Lee ,  Jayesh R. Bhakta

IPC: G06F12/00 ,  G11C8/12 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06

Abstract: A memory module comprises dynamic random access memory (DRAM) devices arranged in ranks, and a module controller configurable to receive address and control signals for a memory operation, and to output first module control signals to the DRAM devices, causing a selected rank to output or receive N-bit-wide data. The module controller is further configurable to output second module control signals to a plurality of data buffers coupled to the DRAM devices via module data lines. Each respective data buffer includes a n-bit-wide (n

公开(公告)号：US20210240620A1

公开(公告)日：2021-08-05

申请号：US17141978

申请日：2021-01-05

Applicant: NETLIST, INC.

Inventor： Hyun Lee ,  Jayesh R. Bhakta

IPC: G06F12/0802 ,  G11C5/04 ,  G11C29/02 ,  G11C7/10

Abstract: A memory module is operable in a memory system with a memory controller. The memory module comprises a module control device to receive command signals and a system clock from the memory controller and to output a module clock, module C/A signals and data buffer control signals. The module C/A signals are provided to memory devices organized in one or more ranks, while the data buffer control signals, together with the module clock, are provided to a plurality of buffer circuits corresponding to respective groups of memory devices and are used to control data paths in the buffer circuits. The plurality of buffer circuits include clock regeneration circuits to regenerate clock signals with programmable delays from the module clock. The regenerated clock signals are provided to respective groups of memory devices so as to locally sync the buffer circuits with respective groups of memory devices.

公开(公告)号：US20210149829A1

公开(公告)日：2021-05-20

申请号：US17114478

申请日：2020-12-07

Applicant: Netlist, Inc.

Inventor： Hyun Lee ,  Jayesh R. Bhakta

IPC: G06F13/16 ,  G06F3/06 ,  G11C5/04 ,  G11C7/10 ,  G11C29/02 ,  G11C16/00 ,  G06F1/10 ,  G06F13/28 ,  G06F13/40 ,  G11C8/18

Abstract: A memory module is operable in a memory system with a memory controller. The memory module comprises memory devices, a module control circuit, and a plurality of buffer circuits coupled between respective sets of data signal lines in a data bus and respective sets of the memory devices. Each respective buffer circuit is mounted on the module board and coupled between a respective set of data signal lines and a respective set of memory devices. Each respective buffer circuit is configured to receive the module control signals and the module clock signal, and to buffer a respective set of data signals in response to the module control signals and the module clock signal. Each respective buffer circuit includes a delay circuit configured to delay the respective set of data signals by an amount determined based on at least one of the module control signals.

公开(公告)号：US09563587B2

公开(公告)日：2017-02-07

申请号：US14846993

申请日：2015-09-07

Applicant: Netlist, Inc.

Inventor： Hyun Lee ,  Jayesh R. Bhakta

IPC: G06F3/00 ,  G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F3/06 ,  G11C16/00 ,  G11C5/04 ,  G11C7/10 ,  G06F1/10 ,  G06F13/40 ,  G11C8/12

CPC classification number: G06F13/1673 ,  G06F1/10 ,  G06F3/0613 ,  G06F3/0647 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0683 ,  G06F13/1642 ,  G06F13/28 ,  G06F13/4027 ,  G11C5/04 ,  G11C7/1006 ,  G11C7/1066 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/20 ,  G11C8/12 ,  G11C8/18 ,  G11C16/00 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/0407

Abstract: A memory module is operatable in a memory system with a memory controller. The memory module comprises a module control device to receive command signals from the memory controller and to output module command signals and module control signals. The module command signals are provided to memory devices organized in groups, each group including at least one memory device, while the module control signals are provided to a plurality of buffer circuits to control data paths in the buffer circuits. The plurality of buffer circuits are associated with respective groups of memory devices and are distributed across a surface of the memory module such that each module control signal arrives at the plurality of buffer circuits at different points in time. The plurality of buffer circuits are configured to align read data signals received from the memory devices such that the read data signals are transmitted to the memory controller from the memory module substantially aligned with each other and in accordance with a read latency parameter of the memory system.

Abstract translation: 存储器模块可在具有存储器控制器的存储器系统中操作。 存储器模块包括一个模块控制装置，用于从存储器控制器接收命令信号并输出​​模块命令信号和模块控制信号。 将模块命令信号提供给组织组织的存储器件，每个组包括至少一个存储器件，同时将模块控制信号提供给多个缓冲电路以控制缓冲电路中的数据路径。 多个缓冲电路与各组存储器件相关联，并且分布在存储器模块的表面上，使得每个模块控制信号在不同的时间点到达多个缓冲电路。 多个缓冲电路被配置为对从存储器件接收的读取数据信号进行对准，使得读取的数据信号从存储器模块传输到存储器模块，该存储器模块基本上彼此对准，并且根据存储器系统的读延迟参数 。

公开(公告)号：US09128632B2

公开(公告)日：2015-09-08

申请号：US13952599

申请日：2013-07-27

Applicant: Netlist, Inc.

Inventor： Hyun Lee ,  Jayesh R. Bhakta

IPC: G06F3/00 ,  G06F12/00 ,  G06F13/00 ,  G06F3/06

CPC classification number: G06F13/1673 ,  G06F1/10 ,  G06F3/0613 ,  G06F3/0647 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0683 ,  G06F13/1642 ,  G06F13/28 ,  G06F13/4027 ,  G11C5/04 ,  G11C7/1006 ,  G11C7/1066 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/20 ,  G11C8/12 ,  G11C8/18 ,  G11C16/00 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/0407

Abstract: A memory module is operatable in a memory system with a memory controller. The memory module comprises a module control device to receive command signals from the memory controller and to output module command signals and module control signals. The module command signals are provided to memory devices organized in groups, each group including at least one memory device, while the module control signals are provided to a plurality of buffer circuits to control data paths in the buffer circuits. The plurality of buffer circuits are associated with respective groups of memory devices and are distributed across a surface of the memory module such that each module control signal arrives at the plurality of buffer circuits at different points in time. The plurality of buffer circuits are configured to align read data signals received from the memory devices such that the read data signals are transmitted to the memory controller from the memory module substantially aligned with each other and in accordance with a read latency parameter of the memory system.

Abstract translation: 存储器模块可在具有存储器控制器的存储器系统中操作。 存储器模块包括一个模块控制装置，用于从存储器控制器接收命令信号并输出​​模块命令信号和模块控制信号。 将模块命令信号提供给以组为单位的存储器件，每个组包括至少一个存储器件，同时将模块控制信号提供给多个缓冲电路以控制缓冲电路中的数据路径。 多个缓冲电路与各组存储器件相关联，并且分布在存储器模块的表面上，使得每个模块控制信号在不同的时间点到达多个缓冲电路。 多个缓冲电路被配置为对从存储器件接收到的读取数据信号进行对准，使得读取的数据信号从存储器模块传输到存储器模块，该存储器模块基本上彼此对齐，并且根据存储器系统的读延迟参数 。

公开(公告)号：US09037774B2

公开(公告)日：2015-05-19

申请号：US13971231

申请日：2013-08-20

Applicant: Netlist, Inc.

Inventor： Jefferey C. Solomon ,  Jayesh R. Bhakta

IPC: G06F12/00 ,  G11C5/04 ,  G06F13/00

CPC classification number: G06F13/1673 ,  G06F12/00 ,  G06F13/00 ,  G06F13/4243 ,  G06F13/4282 ,  G11C5/04 ,  G11C7/1072 ,  G11C15/00

Abstract: A memory module includes a plurality of memory devices and is operable in a computer system to perform memory operations in response to memory commands from a memory controller of the computer system. The memory module comprises a register device configured to receive a set of input control/address signals associated with a respective memory command (e.g., a read command or a write command) from the memory controller and to generate a set of output control/address signals in response to the set of input control/address signals. The set of output control/address signals are provided to the plurality of memory devices. The memory module further comprises a circuit to selectively isolate one or more first memory devices among the plurality of memory devices from the memory controller in response to the respective memory command so as to reduce a load of the memory module to the computer system while one or more second memory devices among the plurality of memory devices are communicating with the memory controller in response to the set of output control/address signals.

Abstract translation: 存储器模块包括多个存储器设备，并且可在计算机系统中操作以响应于来自计算机系统的存储器控​​制器的存储器命令来执行存储器操作。 存储器模块包括寄存器装置，其被配置为从存储器控制器接收与相应存储器命令（例如，读取命令或写入命令）相关联的一组输入控制/地址信号，并且生成一组输出控制/地址信号 响应于该组输入控制/地址信号。 输出控制/地址信号组被提供给多个存储器件。 存储器模块还包括电路，用于响应于相应的存储器命令，选择性地将多个存储器件中的一个或多个第一存储器件与存储器控制器隔离开来，以便将存储器模块的负载减小到计算机系统，同时， 响应于该组输出控制/地址信号，多个存储器件中的更多的第二存储器件正在与存储器控制器进行通信。

公开(公告)号：US20140337539A1

公开(公告)日：2014-11-13

申请号：US13952599

申请日：2013-07-27

Applicant: Netlist, Inc.

Inventor： Hyun Lee ,  Jayesh R. Bhakta

IPC: G06F1/10 ,  G06F3/06

CPC classification number: G06F13/1673 ,  G06F1/10 ,  G06F3/0613 ,  G06F3/0647 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0683 ,  G06F13/1642 ,  G06F13/28 ,  G06F13/4027 ,  G11C5/04 ,  G11C7/1006 ,  G11C7/1066 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/20 ,  G11C8/12 ,  G11C8/18 ,  G11C16/00 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/0407

Abstract: A memory module is operatable in a memory system with a memory controller. The memory module comprises a module control device to receive command signals from the memory controller and to output module command signals and module control signals. The module command signals are provided to memory devices organized in groups, each group including at least one memory device, while the module control signals are provided to a plurality of buffer circuits to control data paths in the buffer circuits. The plurality of buffer circuits are associated with respective groups of memory devices and are distributed across a surface of the memory module such that each module control signal arrives at the plurality of buffer circuits at different points in time. The plurality of buffer circuits are configured to align read data signals received from the memory devices such that the read data signals are transmitted to the memory controller from the memory module substantially aligned with each other and in accordance with a read latency parameter of the memory system.

Abstract translation: 存储器模块可在具有存储器控制器的存储器系统中操作。 存储器模块包括一个模块控制装置，用于从存储器控制器接收命令信号并输出​​模块命令信号和模块控制信号。 将模块命令信号提供给组织组织的存储器件，每个组包括至少一个存储器件，同时将模块控制信号提供给多个缓冲电路以控制缓冲电路中的数据路径。 多个缓冲电路与各组存储器件相关联，并且分布在存储器模块的表面上，使得每个模块控制信号在不同的时间点到达多个缓冲电路。 多个缓冲电路被配置为对从存储器件接收到的读取数据信号进行对准，使得读取的数据信号从存储器模块传输到存储器模块，该存储器模块基本上彼此对齐，并且根据存储器系统的读延迟参数 。

公开(公告)号：US08864500B1

公开(公告)日：2014-10-21

申请号：US13653254

申请日：2012-10-16

Applicant: Netlist, Inc.

Inventor： Jayesh R. Bhakta ,  Enchao Yu ,  Chi She Chen ,  Richard E. Flaig

IPC: H01R12/00

CPC classification number: H05K1/147 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H05K1/0203 ,  H05K1/141 ,  H05K3/4691 ,  H05K2201/10159 ,  H05K2201/1056 ,  H05K2203/1572 ,  H01L2224/0401

Abstract: An electronic module for a computer system comprises a first circuit board having a plurality of edge connectors configured to releasably connect to electrical contacts of a computer system socket, a second circuit board having a plurality of contacts configured to connect with a plurality of electrical components, and a flexible portion having electrical conduits to provide electrical connection between the plurality of edge connectors and the plurality of contacts. The flexible portion further includes an electrically conductive layer extending across a region of the flexible portion. The electrically conductive layer is superposed with the electrical conduits and separated from electrical conduits by a dielectric layer.

Abstract translation: 一种用于计算机系统的电子模块，包括具有多个边缘连接器的第一电路板，所述多个边缘连接器被配置为可释放地连接到计算机系统插座的电触头，第二电路板具有被配置为与多个电气部件连接的多个触点， 以及具有电导管以在所述多个边缘连接器和所述多个触点之间提供电连接的柔性部分。 柔性部分还包括延伸穿过柔性部分的区域的导电层。 导电层与电导管叠合并通过电介质层与电导管分离。

公开(公告)号：US20140040569A1

公开(公告)日：2014-02-06

申请号：US13971231

申请日：2013-08-20

Applicant: Netlist, Inc.

Inventor： Jefferey C. Solomon ,  Jayesh R. Bhakta

IPC: G06F12/00

CPC classification number: G06F13/1673 ,  G06F12/00 ,  G06F13/00 ,  G06F13/4243 ,  G06F13/4282 ,  G11C5/04 ,  G11C7/1072 ,  G11C15/00

Abstract: A circuit is mountable on a memory module that includes a plurality of memory devices and that is operable in a computer system to perform memory operations in response to memory commands from a memory controller. The circuit comprises a register device configured to receive a set of input control/address signals associated with a respective memory command (e.g., a read command or a write command) from the memory controller and to generate a set of output control/address signals in response to the set of input control/address signals. The set of output control/address signals are provided to the plurality of memory devices. The circuit further comprises logic to monitor the memory commands from the memory controller and to selectively isolate one or more first memory devices among the plurality of memory devices from the memory controller in response to the respective memory command so as to reduce a load of the memory module to the computer system while one or more second memory devices among the plurality of memory devices are communicating with the memory controller in response to the set of output control/address signals.

Abstract translation: 电路可安装在包括多个存储器设备的存储器模块上，并且可在计算机系统中操作以响应于来自存储器控制器的存储器命令执行存储器操作。 电路包括寄存器装置，其被配置为从存储器控制器接收与相应存储器命令相关联的一组输入控制/地址信号（例如，读取命令或写入命令），并且生成一组输出控制/地址信号 响应一组输入控制/地址信号。 输出控制/地址信号组被提供给多个存储器件。 该电路还包括用于监视来自存储器控制器的存储器命令的逻辑，并且响应于相应的存储器命令，选择性地将多个存储器件中的一个或多个第一存储器件与存储器控制器隔离，以便减少存储器的负载 模块连接到计算机系统，而多个存储器件中的一个或多个第二存储器件响应于该组输出控制/地址信号而与存储器控制器进行通信。